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5544c1 |
From 3ec8ca067ea6617b5bd4423d0b40c894b39a4924 Mon Sep 17 00:00:00 2001
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5544c1 |
From: Blue Swirl <blauwirbel@gmail.com>
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Date: Sun, 2 Sep 2012 15:28:56 +0000
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Subject: [PATCH] Remove unused CONFIG_TCG_PASS_AREG0 and dead code
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5544c1 |
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Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,
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5544c1 |
remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.
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5544c1 |
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Remove dyngen-exec.h and all references to it. Although included by
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hw/spapr_hcall.c, it does not seem to use it.
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Remove unused HELPER_CFLAGS.
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Reviewed-by: Richard Henderson <rth@twiddle.net>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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Makefile.target | 8 ------
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configure | 11 -------
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cpu-all.h | 11 -------
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cputlb.c | 5 ----
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dyngen-exec.h | 70 --------------------------------------------
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exec-all.h | 4 ---
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hw/spapr_hcall.c | 1 -
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softmmu_defs.h | 21 --------------
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softmmu_header.h | 63 +++++++++++++---------------------------
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softmmu_template.h | 72 +++++++++++++++++-----------------------------
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target-m68k/op_helper.c | 3 --
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target-sparc/Makefile.objs | 2 --
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tcg/arm/tcg-target.c | 31 ++------------------
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tcg/arm/tcg-target.h | 1 -
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tcg/hppa/tcg-target.c | 24 ----------------
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tcg/hppa/tcg-target.h | 1 -
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tcg/i386/tcg-target.c | 30 -------------------
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tcg/i386/tcg-target.h | 1 -
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tcg/ia64/tcg-target.c | 34 ----------------------
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tcg/ia64/tcg-target.h | 1 -
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tcg/mips/tcg-target.c | 31 ++------------------
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tcg/mips/tcg-target.h | 1 -
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tcg/ppc/tcg-target.c | 38 ------------------------
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tcg/ppc64/tcg-target.c | 28 ------------------
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tcg/s390/tcg-target.c | 24 ----------------
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tcg/s390/tcg-target.h | 1 -
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tcg/sparc/tcg-target.c | 30 -------------------
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tcg/sparc/tcg-target.h | 1 -
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tcg/tci/tcg-target.c | 4 ---
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tci.c | 12 --------
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user-exec.c | 14 ---------
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31 files changed, 53 insertions(+), 525 deletions(-)
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delete mode 100644 dyngen-exec.h
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5544c1 |
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diff --git a/Makefile.target b/Makefile.target
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index 7892a8d..d9d54b8 100644
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--- a/Makefile.target
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+++ b/Makefile.target
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@@ -80,14 +80,6 @@ obj-$(CONFIG_GDBSTUB_XML) += gdbstub-xml.o
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tci-dis.o: QEMU_CFLAGS += -I$(SRC_PATH)/tcg -I$(SRC_PATH)/tcg/tci
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5544c1 |
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-# HELPER_CFLAGS is used for all the legacy code compiled with static register
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-# variables
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-user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
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-
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-# Note: this is a workaround. The real fix is to avoid compiling
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-# cpu_signal_handler() in user-exec.c.
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-%/signal.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
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-
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#########################################################
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# Linux user emulator target
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diff --git a/configure b/configure
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index 83b068d..816f0f9 100755
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--- a/configure
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+++ b/configure
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@@ -118,7 +118,6 @@ audio_card_list="ac97 es1370 sb16 hda"
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audio_possible_cards="ac97 es1370 sb16 cs4231a adlib gus hda"
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block_drv_whitelist=""
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host_cc="gcc"
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-helper_cflags=""
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libs_softmmu=""
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libs_tools=""
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audio_pt_int=""
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@@ -904,7 +903,6 @@ case "$cpu" in
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QEMU_CFLAGS="-m32 -ffixed-g2 -ffixed-g3 $QEMU_CFLAGS"
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if test "$solaris" = "no" ; then
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QEMU_CFLAGS="-ffixed-g1 -ffixed-g6 $QEMU_CFLAGS"
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- helper_cflags="-ffixed-i0"
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fi
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;;
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sparc64)
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@@ -929,7 +927,6 @@ case "$cpu" in
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QEMU_CFLAGS="-m32 $QEMU_CFLAGS"
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LDFLAGS="-m32 $LDFLAGS"
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cc_i386='$(CC) -m32'
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- helper_cflags="-fomit-frame-pointer"
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host_guest_base="yes"
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;;
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x86_64)
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@@ -3582,7 +3579,6 @@ if test "$sparse" = "yes" ; then
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echo "HOST_CC := REAL_CC=\"\$(HOST_CC)\" cgcc" >> $config_host_mak
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echo "QEMU_CFLAGS += -Wbitwise -Wno-transparent-union -Wno-old-initializer -Wno-non-pointer-null" >> $config_host_mak
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fi
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-echo "HELPER_CFLAGS=$helper_cflags" >> $config_host_mak
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echo "LDFLAGS=$LDFLAGS" >> $config_host_mak
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echo "ARLIBS_BEGIN=$arlibs_begin" >> $config_host_mak
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echo "ARLIBS_END=$arlibs_end" >> $config_host_mak
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@@ -3837,13 +3833,6 @@ fi
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symlink "$source_path/Makefile.target" "$target_dir/Makefile"
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-
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-case "$target_arch2" in
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- alpha | arm* | cris | i386 | lm32 | m68k | microblaze* | mips* | or32 | s390x | sh4* | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
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- echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
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- ;;
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-esac
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-
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upper() {
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echo "$@"| LC_ALL=C tr '[a-z]' '[A-Z]'
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}
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diff --git a/cpu-all.h b/cpu-all.h
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index 5e07d28..74d3681 100644
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--- a/cpu-all.h
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+++ b/cpu-all.h
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@@ -260,14 +260,6 @@ extern unsigned long reserved_va;
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#define stfl(p, v) stfl_raw(p, v)
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#define stfq(p, v) stfq_raw(p, v)
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-#ifndef CONFIG_TCG_PASS_AREG0
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-#define ldub_code(p) ldub_raw(p)
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-#define ldsb_code(p) ldsb_raw(p)
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-#define lduw_code(p) lduw_raw(p)
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-#define ldsw_code(p) ldsw_raw(p)
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-#define ldl_code(p) ldl_raw(p)
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-#define ldq_code(p) ldq_raw(p)
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-#else
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#define cpu_ldub_code(env1, p) ldub_raw(p)
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#define cpu_ldsb_code(env1, p) ldsb_raw(p)
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#define cpu_lduw_code(env1, p) lduw_raw(p)
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@@ -296,7 +288,6 @@ extern unsigned long reserved_va;
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#define cpu_stw_kernel(env, addr, data) stw_raw(addr, data)
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#define cpu_stl_kernel(env, addr, data) stl_raw(addr, data)
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#define cpu_stq_kernel(env, addr, data) stq_raw(addr, data)
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-#endif
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#define ldub_kernel(p) ldub_raw(p)
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#define ldsb_kernel(p) ldsb_raw(p)
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@@ -313,7 +304,6 @@ extern unsigned long reserved_va;
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#define stfl_kernel(p, v) stfl_raw(p, v)
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#define stfq_kernel(p, vt) stfq_raw(p, v)
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-#ifdef CONFIG_TCG_PASS_AREG0
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#define cpu_ldub_data(env, addr) ldub_raw(addr)
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#define cpu_lduw_data(env, addr) lduw_raw(addr)
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#define cpu_ldl_data(env, addr) ldl_raw(addr)
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@@ -321,7 +311,6 @@ extern unsigned long reserved_va;
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#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
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#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
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#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
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-#endif
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#endif /* defined(CONFIG_USER_ONLY) */
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5544c1 |
/* page related stuff */
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diff --git a/cputlb.c b/cputlb.c
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index d3e7b25..51b5897 100644
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--- a/cputlb.c
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+++ b/cputlb.c
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@@ -325,11 +325,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
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mmu_idx = cpu_mmu_index(env1);
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if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
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(addr & TARGET_PAGE_MASK))) {
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-#ifdef CONFIG_TCG_PASS_AREG0
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cpu_ldub_code(env1, addr);
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-#else
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- ldub_code(addr);
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-#endif
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}
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pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
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mr = iotlb_to_region(pd);
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@@ -348,7 +344,6 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
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#define MMUSUFFIX _cmmu
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#undef GETPC
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#define GETPC() ((uintptr_t)0)
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-#define env cpu_single_env
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5544c1 |
#define SOFTMMU_CODE_ACCESS
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5544c1 |
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5544c1 |
#define SHIFT 0
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5544c1 |
diff --git a/dyngen-exec.h b/dyngen-exec.h
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5544c1 |
deleted file mode 100644
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index 083e20b..0000000
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--- a/dyngen-exec.h
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5544c1 |
+++ /dev/null
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5544c1 |
@@ -1,70 +0,0 @@
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5544c1 |
-/*
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5544c1 |
- * dyngen defines for micro operation code
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5544c1 |
- *
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- * Copyright (c) 2003 Fabrice Bellard
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- *
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5544c1 |
- * This library is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU Lesser General Public
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5544c1 |
- * License as published by the Free Software Foundation; either
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5544c1 |
- * version 2 of the License, or (at your option) any later version.
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5544c1 |
- *
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- * This library is distributed in the hope that it will be useful,
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5544c1 |
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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5544c1 |
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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5544c1 |
- * Lesser General Public License for more details.
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5544c1 |
- *
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- * You should have received a copy of the GNU Lesser General Public
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- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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5544c1 |
- */
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5544c1 |
-#if !defined(__DYNGEN_EXEC_H__)
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5544c1 |
-#define __DYNGEN_EXEC_H__
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5544c1 |
-
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5544c1 |
-#if defined(CONFIG_TCG_INTERPRETER)
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5544c1 |
-/* The TCG interpreter does not need a special register AREG0,
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5544c1 |
- * but it is possible to use one by defining AREG0.
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5544c1 |
- * On i386, register edi seems to work. */
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5544c1 |
-/* Run without special register AREG0 or use a value defined elsewhere. */
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5544c1 |
-#elif defined(__i386__)
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5544c1 |
-#define AREG0 "ebp"
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5544c1 |
-#elif defined(__x86_64__)
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5544c1 |
-#define AREG0 "r14"
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5544c1 |
-#elif defined(_ARCH_PPC)
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5544c1 |
-#define AREG0 "r27"
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5544c1 |
-#elif defined(__arm__)
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5544c1 |
-#define AREG0 "r6"
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5544c1 |
-#elif defined(__hppa__)
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5544c1 |
-#define AREG0 "r17"
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5544c1 |
-#elif defined(__mips__)
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5544c1 |
-#define AREG0 "s0"
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5544c1 |
-#elif defined(__sparc__)
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5544c1 |
-#ifdef CONFIG_SOLARIS
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5544c1 |
-#define AREG0 "g2"
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5544c1 |
-#else
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5544c1 |
-#ifdef __sparc_v9__
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5544c1 |
-#define AREG0 "g5"
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5544c1 |
-#else
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5544c1 |
-#define AREG0 "g6"
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5544c1 |
-#endif
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5544c1 |
-#endif
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5544c1 |
-#elif defined(__s390__)
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5544c1 |
-#define AREG0 "r10"
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5544c1 |
-#elif defined(__alpha__)
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5544c1 |
-/* Note $15 is the frame pointer, so anything in op-i386.c that would
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5544c1 |
- require a frame pointer, like alloca, would probably loose. */
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5544c1 |
-#define AREG0 "$15"
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5544c1 |
-#elif defined(__mc68000)
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5544c1 |
-#define AREG0 "%a5"
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5544c1 |
-#elif defined(__ia64__)
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5544c1 |
-#define AREG0 "r7"
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5544c1 |
-#else
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5544c1 |
-#error unsupported CPU
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5544c1 |
-#endif
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5544c1 |
-
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5544c1 |
-#if defined(AREG0)
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5544c1 |
-register CPUArchState *env asm(AREG0);
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5544c1 |
-#else
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5544c1 |
-/* TODO: Try env = cpu_single_env. */
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5544c1 |
-extern CPUArchState *env;
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5544c1 |
-#endif
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5544c1 |
-
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5544c1 |
-#endif /* !defined(__DYNGEN_EXEC_H__) */
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5544c1 |
diff --git a/exec-all.h b/exec-all.h
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5544c1 |
index c5ec8e1..c5d3a13 100644
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5544c1 |
--- a/exec-all.h
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5544c1 |
+++ b/exec-all.h
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5544c1 |
@@ -323,9 +323,6 @@ void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
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5544c1 |
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5544c1 |
#define ACCESS_TYPE (NB_MMU_MODES + 1)
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5544c1 |
#define MEMSUFFIX _code
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5544c1 |
-#ifndef CONFIG_TCG_PASS_AREG0
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5544c1 |
-#define env cpu_single_env
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
#define DATA_SIZE 1
|
|
|
5544c1 |
#include "softmmu_header.h"
|
|
|
5544c1 |
@@ -341,7 +338,6 @@ void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
|
|
|
5544c1 |
|
|
|
5544c1 |
#undef ACCESS_TYPE
|
|
|
5544c1 |
#undef MEMSUFFIX
|
|
|
5544c1 |
-#undef env
|
|
|
5544c1 |
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c
|
|
|
5544c1 |
index a5990a9..abd847f 100644
|
|
|
5544c1 |
--- a/hw/spapr_hcall.c
|
|
|
5544c1 |
+++ b/hw/spapr_hcall.c
|
|
|
5544c1 |
@@ -1,6 +1,5 @@
|
|
|
5544c1 |
#include "sysemu.h"
|
|
|
5544c1 |
#include "cpu.h"
|
|
|
5544c1 |
-#include "dyngen-exec.h"
|
|
|
5544c1 |
#include "qemu-char.h"
|
|
|
5544c1 |
#include "sysemu.h"
|
|
|
5544c1 |
#include "qemu-char.h"
|
|
|
5544c1 |
diff --git a/softmmu_defs.h b/softmmu_defs.h
|
|
|
5544c1 |
index 8d59f9d..1f25e33 100644
|
|
|
5544c1 |
--- a/softmmu_defs.h
|
|
|
5544c1 |
+++ b/softmmu_defs.h
|
|
|
5544c1 |
@@ -9,25 +9,6 @@
|
|
|
5544c1 |
#ifndef SOFTMMU_DEFS_H
|
|
|
5544c1 |
#define SOFTMMU_DEFS_H
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifndef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
-uint8_t __ldb_mmu(target_ulong addr, int mmu_idx);
|
|
|
5544c1 |
-void __stb_mmu(target_ulong addr, uint8_t val, int mmu_idx);
|
|
|
5544c1 |
-uint16_t __ldw_mmu(target_ulong addr, int mmu_idx);
|
|
|
5544c1 |
-void __stw_mmu(target_ulong addr, uint16_t val, int mmu_idx);
|
|
|
5544c1 |
-uint32_t __ldl_mmu(target_ulong addr, int mmu_idx);
|
|
|
5544c1 |
-void __stl_mmu(target_ulong addr, uint32_t val, int mmu_idx);
|
|
|
5544c1 |
-uint64_t __ldq_mmu(target_ulong addr, int mmu_idx);
|
|
|
5544c1 |
-void __stq_mmu(target_ulong addr, uint64_t val, int mmu_idx);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-uint8_t __ldb_cmmu(target_ulong addr, int mmu_idx);
|
|
|
5544c1 |
-void __stb_cmmu(target_ulong addr, uint8_t val, int mmu_idx);
|
|
|
5544c1 |
-uint16_t __ldw_cmmu(target_ulong addr, int mmu_idx);
|
|
|
5544c1 |
-void __stw_cmmu(target_ulong addr, uint16_t val, int mmu_idx);
|
|
|
5544c1 |
-uint32_t __ldl_cmmu(target_ulong addr, int mmu_idx);
|
|
|
5544c1 |
-void __stl_cmmu(target_ulong addr, uint32_t val, int mmu_idx);
|
|
|
5544c1 |
-uint64_t __ldq_cmmu(target_ulong addr, int mmu_idx);
|
|
|
5544c1 |
-void __stq_cmmu(target_ulong addr, uint64_t val, int mmu_idx);
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
uint8_t helper_ldb_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
|
|
|
5544c1 |
void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
|
|
|
5544c1 |
int mmu_idx);
|
|
|
5544c1 |
@@ -54,5 +35,3 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
|
|
|
5544c1 |
void helper_stq_cmmu(CPUArchState *env, target_ulong addr, uint64_t val,
|
|
|
5544c1 |
int mmu_idx);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
diff --git a/softmmu_header.h b/softmmu_header.h
|
|
|
5544c1 |
index cf1aa38..d8d9c81 100644
|
|
|
5544c1 |
--- a/softmmu_header.h
|
|
|
5544c1 |
+++ b/softmmu_header.h
|
|
|
5544c1 |
@@ -78,23 +78,10 @@
|
|
|
5544c1 |
#define ADDR_READ addr_read
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifndef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
-#define ENV_PARAM
|
|
|
5544c1 |
-#define ENV_VAR
|
|
|
5544c1 |
-#define CPU_PREFIX
|
|
|
5544c1 |
-#define HELPER_PREFIX __
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-#define ENV_PARAM CPUArchState *env,
|
|
|
5544c1 |
-#define ENV_VAR env,
|
|
|
5544c1 |
-#define CPU_PREFIX cpu_
|
|
|
5544c1 |
-#define HELPER_PREFIX helper_
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
-
|
|
|
5544c1 |
/* generic load/store macros */
|
|
|
5544c1 |
|
|
|
5544c1 |
static inline RES_TYPE
|
|
|
5544c1 |
-glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
- target_ulong ptr)
|
|
|
5544c1 |
+glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int page_index;
|
|
|
5544c1 |
RES_TYPE res;
|
|
|
5544c1 |
@@ -106,9 +93,7 @@ glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
mmu_idx = CPU_MMU_INDEX;
|
|
|
5544c1 |
if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
|
|
|
5544c1 |
(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
|
|
|
5544c1 |
- res = glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_VAR
|
|
|
5544c1 |
- addr,
|
|
|
5544c1 |
- mmu_idx);
|
|
|
5544c1 |
+ res = glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx);
|
|
|
5544c1 |
} else {
|
|
|
5544c1 |
uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
|
|
|
5544c1 |
res = glue(glue(ld, USUFFIX), _raw)(hostaddr);
|
|
|
5544c1 |
@@ -118,8 +103,7 @@ glue(glue(glue(CPU_PREFIX, ld), USUFFIX), MEMSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
|
|
|
5544c1 |
#if DATA_SIZE <= 2
|
|
|
5544c1 |
static inline int
|
|
|
5544c1 |
-glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
- target_ulong ptr)
|
|
|
5544c1 |
+glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int res, page_index;
|
|
|
5544c1 |
target_ulong addr;
|
|
|
5544c1 |
@@ -130,8 +114,8 @@ glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
mmu_idx = CPU_MMU_INDEX;
|
|
|
5544c1 |
if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
|
|
|
5544c1 |
(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
|
|
|
5544c1 |
- res = (DATA_STYPE)glue(glue(glue(HELPER_PREFIX, ld), SUFFIX),
|
|
|
5544c1 |
- MMUSUFFIX)(ENV_VAR addr, mmu_idx);
|
|
|
5544c1 |
+ res = (DATA_STYPE)glue(glue(helper_ld, SUFFIX),
|
|
|
5544c1 |
+ MMUSUFFIX)(env, addr, mmu_idx);
|
|
|
5544c1 |
} else {
|
|
|
5544c1 |
uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
|
|
|
5544c1 |
res = glue(glue(lds, SUFFIX), _raw)(hostaddr);
|
|
|
5544c1 |
@@ -145,8 +129,8 @@ glue(glue(glue(CPU_PREFIX, lds), SUFFIX), MEMSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
/* generic store macro */
|
|
|
5544c1 |
|
|
|
5544c1 |
static inline void
|
|
|
5544c1 |
-glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr,
|
|
|
5544c1 |
- RES_TYPE v)
|
|
|
5544c1 |
+glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,
|
|
|
5544c1 |
+ RES_TYPE v)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
int page_index;
|
|
|
5544c1 |
target_ulong addr;
|
|
|
5544c1 |
@@ -157,8 +141,7 @@ glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr,
|
|
|
5544c1 |
mmu_idx = CPU_MMU_INDEX;
|
|
|
5544c1 |
if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
|
|
|
5544c1 |
(addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
|
|
|
5544c1 |
- glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_VAR addr, v,
|
|
|
5544c1 |
- mmu_idx);
|
|
|
5544c1 |
+ glue(glue(helper_st, SUFFIX), MMUSUFFIX)(env, addr, v, mmu_idx);
|
|
|
5544c1 |
} else {
|
|
|
5544c1 |
uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
|
|
|
5544c1 |
glue(glue(st, SUFFIX), _raw)(hostaddr, v);
|
|
|
5544c1 |
@@ -170,52 +153,50 @@ glue(glue(glue(CPU_PREFIX, st), SUFFIX), MEMSUFFIX)(ENV_PARAM target_ulong ptr,
|
|
|
5544c1 |
#if ACCESS_TYPE != (NB_MMU_MODES + 1)
|
|
|
5544c1 |
|
|
|
5544c1 |
#if DATA_SIZE == 8
|
|
|
5544c1 |
-static inline float64 glue(glue(CPU_PREFIX, ldfq), MEMSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
- target_ulong ptr)
|
|
|
5544c1 |
+static inline float64 glue(cpu_ldfq, MEMSUFFIX)(CPUArchState *env,
|
|
|
5544c1 |
+ target_ulong ptr)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
union {
|
|
|
5544c1 |
float64 d;
|
|
|
5544c1 |
uint64_t i;
|
|
|
5544c1 |
} u;
|
|
|
5544c1 |
- u.i = glue(glue(CPU_PREFIX, ldq), MEMSUFFIX)(ENV_VAR ptr);
|
|
|
5544c1 |
+ u.i = glue(cpu_ldq, MEMSUFFIX)(env, ptr);
|
|
|
5544c1 |
return u.d;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static inline void glue(glue(CPU_PREFIX, stfq), MEMSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
- target_ulong ptr,
|
|
|
5544c1 |
- float64 v)
|
|
|
5544c1 |
+static inline void glue(cpu_stfq, MEMSUFFIX)(CPUArchState *env,
|
|
|
5544c1 |
+ target_ulong ptr, float64 v)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
union {
|
|
|
5544c1 |
float64 d;
|
|
|
5544c1 |
uint64_t i;
|
|
|
5544c1 |
} u;
|
|
|
5544c1 |
u.d = v;
|
|
|
5544c1 |
- glue(glue(CPU_PREFIX, stq), MEMSUFFIX)(ENV_VAR ptr, u.i);
|
|
|
5544c1 |
+ glue(cpu_stq, MEMSUFFIX)(env, ptr, u.i);
|
|
|
5544c1 |
}
|
|
|
5544c1 |
#endif /* DATA_SIZE == 8 */
|
|
|
5544c1 |
|
|
|
5544c1 |
#if DATA_SIZE == 4
|
|
|
5544c1 |
-static inline float32 glue(glue(CPU_PREFIX, ldfl), MEMSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
- target_ulong ptr)
|
|
|
5544c1 |
+static inline float32 glue(cpu_ldfl, MEMSUFFIX)(CPUArchState *env,
|
|
|
5544c1 |
+ target_ulong ptr)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
union {
|
|
|
5544c1 |
float32 f;
|
|
|
5544c1 |
uint32_t i;
|
|
|
5544c1 |
} u;
|
|
|
5544c1 |
- u.i = glue(glue(CPU_PREFIX, ldl), MEMSUFFIX)(ENV_VAR ptr);
|
|
|
5544c1 |
+ u.i = glue(cpu_ldl, MEMSUFFIX)(env, ptr);
|
|
|
5544c1 |
return u.f;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static inline void glue(glue(CPU_PREFIX, stfl), MEMSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
- target_ulong ptr,
|
|
|
5544c1 |
- float32 v)
|
|
|
5544c1 |
+static inline void glue(cpu_stfl, MEMSUFFIX)(CPUArchState *env,
|
|
|
5544c1 |
+ target_ulong ptr, float32 v)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
union {
|
|
|
5544c1 |
float32 f;
|
|
|
5544c1 |
uint32_t i;
|
|
|
5544c1 |
} u;
|
|
|
5544c1 |
u.f = v;
|
|
|
5544c1 |
- glue(glue(CPU_PREFIX, stl), MEMSUFFIX)(ENV_VAR ptr, u.i);
|
|
|
5544c1 |
+ glue(cpu_stl, MEMSUFFIX)(env, ptr, u.i);
|
|
|
5544c1 |
}
|
|
|
5544c1 |
#endif /* DATA_SIZE == 4 */
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -230,7 +211,3 @@ static inline void glue(glue(CPU_PREFIX, stfl), MEMSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
#undef CPU_MMU_INDEX
|
|
|
5544c1 |
#undef MMUSUFFIX
|
|
|
5544c1 |
#undef ADDR_READ
|
|
|
5544c1 |
-#undef ENV_PARAM
|
|
|
5544c1 |
-#undef ENV_VAR
|
|
|
5544c1 |
-#undef CPU_PREFIX
|
|
|
5544c1 |
-#undef HELPER_PREFIX
|
|
|
5544c1 |
diff --git a/softmmu_template.h b/softmmu_template.h
|
|
|
5544c1 |
index b8bd700..e2490f0 100644
|
|
|
5544c1 |
--- a/softmmu_template.h
|
|
|
5544c1 |
+++ b/softmmu_template.h
|
|
|
5544c1 |
@@ -54,23 +54,11 @@
|
|
|
5544c1 |
#define ADDR_READ addr_read
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifndef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
-#define ENV_PARAM
|
|
|
5544c1 |
-#define ENV_VAR
|
|
|
5544c1 |
-#define CPU_PREFIX
|
|
|
5544c1 |
-#define HELPER_PREFIX __
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-#define ENV_PARAM CPUArchState *env,
|
|
|
5544c1 |
-#define ENV_VAR env,
|
|
|
5544c1 |
-#define CPU_PREFIX cpu_
|
|
|
5544c1 |
-#define HELPER_PREFIX helper_
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
+static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
|
|
|
5544c1 |
target_ulong addr,
|
|
|
5544c1 |
int mmu_idx,
|
|
|
5544c1 |
uintptr_t retaddr);
|
|
|
5544c1 |
-static inline DATA_TYPE glue(io_read, SUFFIX)(ENV_PARAM
|
|
|
5544c1 |
+static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
|
|
|
5544c1 |
target_phys_addr_t physaddr,
|
|
|
5544c1 |
target_ulong addr,
|
|
|
5544c1 |
uintptr_t retaddr)
|
|
|
5544c1 |
@@ -104,9 +92,8 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(ENV_PARAM
|
|
|
5544c1 |
|
|
|
5544c1 |
/* handle all cases except unaligned access which span two pages */
|
|
|
5544c1 |
DATA_TYPE
|
|
|
5544c1 |
-glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
- target_ulong addr,
|
|
|
5544c1 |
- int mmu_idx)
|
|
|
5544c1 |
+glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
|
|
|
5544c1 |
+ int mmu_idx)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
DATA_TYPE res;
|
|
|
5544c1 |
int index;
|
|
|
5544c1 |
@@ -126,15 +113,15 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
goto do_unaligned_access;
|
|
|
5544c1 |
retaddr = GETPC();
|
|
|
5544c1 |
ioaddr = env->iotlb[mmu_idx][index];
|
|
|
5544c1 |
- res = glue(io_read, SUFFIX)(ENV_VAR ioaddr, addr, retaddr);
|
|
|
5544c1 |
+ res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
|
|
|
5544c1 |
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
|
|
|
5544c1 |
/* slow unaligned access (it spans two pages or IO) */
|
|
|
5544c1 |
do_unaligned_access:
|
|
|
5544c1 |
retaddr = GETPC();
|
|
|
5544c1 |
#ifdef ALIGNED_ONLY
|
|
|
5544c1 |
- do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
|
|
|
5544c1 |
+ do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
- res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr,
|
|
|
5544c1 |
+ res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr,
|
|
|
5544c1 |
mmu_idx, retaddr);
|
|
|
5544c1 |
} else {
|
|
|
5544c1 |
/* unaligned/aligned access in the same page */
|
|
|
5544c1 |
@@ -142,7 +129,7 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
#ifdef ALIGNED_ONLY
|
|
|
5544c1 |
if ((addr & (DATA_SIZE - 1)) != 0) {
|
|
|
5544c1 |
retaddr = GETPC();
|
|
|
5544c1 |
- do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
|
|
|
5544c1 |
+ do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
|
|
|
5544c1 |
}
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
addend = env->tlb_table[mmu_idx][index].addend;
|
|
|
5544c1 |
@@ -154,7 +141,7 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
retaddr = GETPC();
|
|
|
5544c1 |
#ifdef ALIGNED_ONLY
|
|
|
5544c1 |
if ((addr & (DATA_SIZE - 1)) != 0)
|
|
|
5544c1 |
- do_unaligned_access(ENV_VAR addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
|
|
|
5544c1 |
+ do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
|
|
|
5544c1 |
goto redo;
|
|
|
5544c1 |
@@ -164,7 +151,7 @@ glue(glue(glue(HELPER_PREFIX, ld), SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
|
|
|
5544c1 |
/* handle all unaligned cases */
|
|
|
5544c1 |
static DATA_TYPE
|
|
|
5544c1 |
-glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
+glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
|
|
|
5544c1 |
target_ulong addr,
|
|
|
5544c1 |
int mmu_idx,
|
|
|
5544c1 |
uintptr_t retaddr)
|
|
|
5544c1 |
@@ -183,15 +170,15 @@ glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
if ((addr & (DATA_SIZE - 1)) != 0)
|
|
|
5544c1 |
goto do_unaligned_access;
|
|
|
5544c1 |
ioaddr = env->iotlb[mmu_idx][index];
|
|
|
5544c1 |
- res = glue(io_read, SUFFIX)(ENV_VAR ioaddr, addr, retaddr);
|
|
|
5544c1 |
+ res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
|
|
|
5544c1 |
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
|
|
|
5544c1 |
do_unaligned_access:
|
|
|
5544c1 |
/* slow unaligned access (it spans two pages) */
|
|
|
5544c1 |
addr1 = addr & ~(DATA_SIZE - 1);
|
|
|
5544c1 |
addr2 = addr1 + DATA_SIZE;
|
|
|
5544c1 |
- res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr1,
|
|
|
5544c1 |
+ res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr1,
|
|
|
5544c1 |
mmu_idx, retaddr);
|
|
|
5544c1 |
- res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_VAR addr2,
|
|
|
5544c1 |
+ res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr2,
|
|
|
5544c1 |
mmu_idx, retaddr);
|
|
|
5544c1 |
shift = (addr & (DATA_SIZE - 1)) * 8;
|
|
|
5544c1 |
#ifdef TARGET_WORDS_BIGENDIAN
|
|
|
5544c1 |
@@ -216,13 +203,13 @@ glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
|
|
|
5544c1 |
#ifndef SOFTMMU_CODE_ACCESS
|
|
|
5544c1 |
|
|
|
5544c1 |
-static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
+static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
|
|
|
5544c1 |
target_ulong addr,
|
|
|
5544c1 |
DATA_TYPE val,
|
|
|
5544c1 |
int mmu_idx,
|
|
|
5544c1 |
uintptr_t retaddr);
|
|
|
5544c1 |
|
|
|
5544c1 |
-static inline void glue(io_write, SUFFIX)(ENV_PARAM
|
|
|
5544c1 |
+static inline void glue(io_write, SUFFIX)(CPUArchState *env,
|
|
|
5544c1 |
target_phys_addr_t physaddr,
|
|
|
5544c1 |
DATA_TYPE val,
|
|
|
5544c1 |
target_ulong addr,
|
|
|
5544c1 |
@@ -253,10 +240,9 @@ static inline void glue(io_write, SUFFIX)(ENV_PARAM
|
|
|
5544c1 |
#endif /* SHIFT > 2 */
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
- target_ulong addr,
|
|
|
5544c1 |
- DATA_TYPE val,
|
|
|
5544c1 |
- int mmu_idx)
|
|
|
5544c1 |
+void glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
|
|
|
5544c1 |
+ target_ulong addr, DATA_TYPE val,
|
|
|
5544c1 |
+ int mmu_idx)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
target_phys_addr_t ioaddr;
|
|
|
5544c1 |
target_ulong tlb_addr;
|
|
|
5544c1 |
@@ -273,14 +259,14 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
goto do_unaligned_access;
|
|
|
5544c1 |
retaddr = GETPC();
|
|
|
5544c1 |
ioaddr = env->iotlb[mmu_idx][index];
|
|
|
5544c1 |
- glue(io_write, SUFFIX)(ENV_VAR ioaddr, val, addr, retaddr);
|
|
|
5544c1 |
+ glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
|
|
|
5544c1 |
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
|
|
|
5544c1 |
do_unaligned_access:
|
|
|
5544c1 |
retaddr = GETPC();
|
|
|
5544c1 |
#ifdef ALIGNED_ONLY
|
|
|
5544c1 |
- do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
|
|
|
5544c1 |
+ do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
- glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_VAR addr, val,
|
|
|
5544c1 |
+ glue(glue(slow_st, SUFFIX), MMUSUFFIX)(env, addr, val,
|
|
|
5544c1 |
mmu_idx, retaddr);
|
|
|
5544c1 |
} else {
|
|
|
5544c1 |
/* aligned/unaligned access in the same page */
|
|
|
5544c1 |
@@ -288,7 +274,7 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
#ifdef ALIGNED_ONLY
|
|
|
5544c1 |
if ((addr & (DATA_SIZE - 1)) != 0) {
|
|
|
5544c1 |
retaddr = GETPC();
|
|
|
5544c1 |
- do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
|
|
|
5544c1 |
+ do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
|
|
|
5544c1 |
}
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
addend = env->tlb_table[mmu_idx][index].addend;
|
|
|
5544c1 |
@@ -300,7 +286,7 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
retaddr = GETPC();
|
|
|
5544c1 |
#ifdef ALIGNED_ONLY
|
|
|
5544c1 |
if ((addr & (DATA_SIZE - 1)) != 0)
|
|
|
5544c1 |
- do_unaligned_access(ENV_VAR addr, 1, mmu_idx, retaddr);
|
|
|
5544c1 |
+ do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
tlb_fill(env, addr, 1, mmu_idx, retaddr);
|
|
|
5544c1 |
goto redo;
|
|
|
5544c1 |
@@ -308,7 +294,7 @@ void glue(glue(glue(HELPER_PREFIX, st), SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
/* handles all unaligned cases */
|
|
|
5544c1 |
-static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
+static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
|
|
|
5544c1 |
target_ulong addr,
|
|
|
5544c1 |
DATA_TYPE val,
|
|
|
5544c1 |
int mmu_idx,
|
|
|
5544c1 |
@@ -327,7 +313,7 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
if ((addr & (DATA_SIZE - 1)) != 0)
|
|
|
5544c1 |
goto do_unaligned_access;
|
|
|
5544c1 |
ioaddr = env->iotlb[mmu_idx][index];
|
|
|
5544c1 |
- glue(io_write, SUFFIX)(ENV_VAR ioaddr, val, addr, retaddr);
|
|
|
5544c1 |
+ glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
|
|
|
5544c1 |
} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
|
|
|
5544c1 |
do_unaligned_access:
|
|
|
5544c1 |
/* XXX: not efficient, but simple */
|
|
|
5544c1 |
@@ -335,11 +321,11 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
* previous page from the TLB cache. */
|
|
|
5544c1 |
for(i = DATA_SIZE - 1; i >= 0; i--) {
|
|
|
5544c1 |
#ifdef TARGET_WORDS_BIGENDIAN
|
|
|
5544c1 |
- glue(slow_stb, MMUSUFFIX)(ENV_VAR addr + i,
|
|
|
5544c1 |
+ glue(slow_stb, MMUSUFFIX)(env, addr + i,
|
|
|
5544c1 |
val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
|
|
|
5544c1 |
mmu_idx, retaddr);
|
|
|
5544c1 |
#else
|
|
|
5544c1 |
- glue(slow_stb, MMUSUFFIX)(ENV_VAR addr + i,
|
|
|
5544c1 |
+ glue(slow_stb, MMUSUFFIX)(env, addr + i,
|
|
|
5544c1 |
val >> (i * 8),
|
|
|
5544c1 |
mmu_idx, retaddr);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
@@ -366,7 +352,3 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(ENV_PARAM
|
|
|
5544c1 |
#undef USUFFIX
|
|
|
5544c1 |
#undef DATA_SIZE
|
|
|
5544c1 |
#undef ADDR_READ
|
|
|
5544c1 |
-#undef ENV_PARAM
|
|
|
5544c1 |
-#undef ENV_VAR
|
|
|
5544c1 |
-#undef CPU_PREFIX
|
|
|
5544c1 |
-#undef HELPER_PREFIX
|
|
|
5544c1 |
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
|
|
|
5544c1 |
index 3116287..aa00504 100644
|
|
|
5544c1 |
--- a/target-m68k/op_helper.c
|
|
|
5544c1 |
+++ b/target-m68k/op_helper.c
|
|
|
5544c1 |
@@ -192,9 +192,6 @@ void HELPER(divu)(CPUM68KState *env, uint32_t word)
|
|
|
5544c1 |
quot = num / den;
|
|
|
5544c1 |
rem = num % den;
|
|
|
5544c1 |
flags = 0;
|
|
|
5544c1 |
- /* Avoid using a PARAM1 of zero. This breaks dyngen because it uses
|
|
|
5544c1 |
- the address of a symbol, and gcc knows symbols can't have address
|
|
|
5544c1 |
- zero. */
|
|
|
5544c1 |
if (word && quot > 0xffff)
|
|
|
5544c1 |
flags |= CCF_V;
|
|
|
5544c1 |
if (quot == 0)
|
|
|
5544c1 |
diff --git a/target-sparc/Makefile.objs b/target-sparc/Makefile.objs
|
|
|
5544c1 |
index a93e07d..9fc42ea 100644
|
|
|
5544c1 |
--- a/target-sparc/Makefile.objs
|
|
|
5544c1 |
+++ b/target-sparc/Makefile.objs
|
|
|
5544c1 |
@@ -4,5 +4,3 @@ obj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
|
|
|
5544c1 |
obj-$(TARGET_SPARC) += int32_helper.o
|
|
|
5544c1 |
obj-$(TARGET_SPARC64) += int64_helper.o
|
|
|
5544c1 |
obj-$(TARGET_SPARC64) += vis_helper.o
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
|
|
|
5544c1 |
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
|
|
|
5544c1 |
index cf0ca3d..aed3b53 100644
|
|
|
5544c1 |
--- a/tcg/arm/tcg-target.c
|
|
|
5544c1 |
+++ b/tcg/arm/tcg-target.c
|
|
|
5544c1 |
@@ -176,7 +176,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
so don't use these. */
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
|
|
|
5544c1 |
-#if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
|
|
|
5544c1 |
+#if TARGET_LONG_BITS == 64
|
|
|
5544c1 |
/* If we're passing env to the helper as r0 and need a regpair
|
|
|
5544c1 |
* for the address then r2 will be overwritten as we're setting
|
|
|
5544c1 |
* up the args to the helper.
|
|
|
5544c1 |
@@ -204,8 +204,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
use these. */
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
|
|
|
5544c1 |
-#if defined(CONFIG_SOFTMMU) && \
|
|
|
5544c1 |
- defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
|
|
|
5544c1 |
+#if defined(CONFIG_SOFTMMU) && (TARGET_LONG_BITS == 64)
|
|
|
5544c1 |
/* Avoid clashes with registers being used for helper args */
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
|
|
|
5544c1 |
@@ -223,7 +222,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
#ifdef CONFIG_SOFTMMU
|
|
|
5544c1 |
/* r2 is still needed to load data_reg, so don't use it. */
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
|
|
|
5544c1 |
-#if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
|
|
|
5544c1 |
+#if TARGET_LONG_BITS == 64
|
|
|
5544c1 |
/* Avoid clashes with registers being used for helper args */
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
@@ -954,7 +953,6 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
|
|
|
5544c1 |
|
|
|
5544c1 |
#include "../../softmmu_defs.h"
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
|
|
|
5544c1 |
int mmu_idx) */
|
|
|
5544c1 |
static const void * const qemu_ld_helpers[4] = {
|
|
|
5544c1 |
@@ -972,25 +970,6 @@ static const void * const qemu_st_helpers[4] = {
|
|
|
5544c1 |
helper_stl_mmu,
|
|
|
5544c1 |
helper_stq_mmu,
|
|
|
5544c1 |
};
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
|
|
|
5544c1 |
- mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_ld_helpers[4] = {
|
|
|
5544c1 |
- __ldb_mmu,
|
|
|
5544c1 |
- __ldw_mmu,
|
|
|
5544c1 |
- __ldl_mmu,
|
|
|
5544c1 |
- __ldq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
|
|
|
5544c1 |
- int mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_st_helpers[4] = {
|
|
|
5544c1 |
- __stb_mmu,
|
|
|
5544c1 |
- __stw_mmu,
|
|
|
5544c1 |
- __stl_mmu,
|
|
|
5544c1 |
- __stq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Helper routines for marshalling helper function arguments into
|
|
|
5544c1 |
* the correct registers and stack.
|
|
|
5544c1 |
@@ -1203,9 +1182,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
* trash by moving the earlier arguments into them.
|
|
|
5544c1 |
*/
|
|
|
5544c1 |
argreg = TCG_REG_R0;
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
#if TARGET_LONG_BITS == 64
|
|
|
5544c1 |
argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
|
|
|
5544c1 |
#else
|
|
|
5544c1 |
@@ -1421,9 +1398,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
* trash by moving the earlier arguments into them.
|
|
|
5544c1 |
*/
|
|
|
5544c1 |
argreg = TCG_REG_R0;
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
#if TARGET_LONG_BITS == 64
|
|
|
5544c1 |
argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
|
|
|
5544c1 |
#else
|
|
|
5544c1 |
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
|
|
|
5544c1 |
index f90b834..c0b8f72 100644
|
|
|
5544c1 |
--- a/tcg/arm/tcg-target.h
|
|
|
5544c1 |
+++ b/tcg/arm/tcg-target.h
|
|
|
5544c1 |
@@ -77,7 +77,6 @@ typedef enum {
|
|
|
5544c1 |
#define TCG_TARGET_HAS_GUEST_BASE
|
|
|
5544c1 |
|
|
|
5544c1 |
enum {
|
|
|
5544c1 |
- /* Note: must be synced with dyngen-exec.h */
|
|
|
5544c1 |
TCG_AREG0 = TCG_REG_R6,
|
|
|
5544c1 |
};
|
|
|
5544c1 |
|
|
|
5544c1 |
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
|
|
|
5544c1 |
index 2885212..8b81b70 100644
|
|
|
5544c1 |
--- a/tcg/hppa/tcg-target.c
|
|
|
5544c1 |
+++ b/tcg/hppa/tcg-target.c
|
|
|
5544c1 |
@@ -882,7 +882,6 @@ static void tcg_out_setcond2(TCGContext *s, int cond, TCGArg ret,
|
|
|
5544c1 |
#if defined(CONFIG_SOFTMMU)
|
|
|
5544c1 |
#include "../../softmmu_defs.h"
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
|
|
|
5544c1 |
int mmu_idx) */
|
|
|
5544c1 |
static const void * const qemu_ld_helpers[4] = {
|
|
|
5544c1 |
@@ -900,25 +899,6 @@ static const void * const qemu_st_helpers[4] = {
|
|
|
5544c1 |
helper_stl_mmu,
|
|
|
5544c1 |
helper_stq_mmu,
|
|
|
5544c1 |
};
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
|
|
|
5544c1 |
- mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_ld_helpers[4] = {
|
|
|
5544c1 |
- __ldb_mmu,
|
|
|
5544c1 |
- __ldw_mmu,
|
|
|
5544c1 |
- __ldl_mmu,
|
|
|
5544c1 |
- __ldq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
|
|
|
5544c1 |
- int mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_st_helpers[4] = {
|
|
|
5544c1 |
- __stb_mmu,
|
|
|
5544c1 |
- __stw_mmu,
|
|
|
5544c1 |
- __stl_mmu,
|
|
|
5544c1 |
- __stq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Load and compare a TLB entry, and branch if TLB miss. OFFSET is set to
|
|
|
5544c1 |
the offset of the first ADDR_READ or ADDR_WRITE member of the appropriate
|
|
|
5544c1 |
@@ -1085,7 +1065,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
tcg_out_movi(s, TCG_TYPE_I32, argreg, mem_index);
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* XXX/FIXME: suboptimal */
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2],
|
|
|
5544c1 |
tcg_target_call_iarg_regs[1]);
|
|
|
5544c1 |
@@ -1093,7 +1072,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
tcg_target_call_iarg_regs[0]);
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
|
|
|
5544c1 |
TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
tcg_out_call(s, qemu_ld_helpers[opc & 3]);
|
|
|
5544c1 |
|
|
|
5544c1 |
switch (opc) {
|
|
|
5544c1 |
@@ -1245,7 +1223,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
tcg_abort();
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* XXX/FIXME: suboptimal */
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
|
|
|
5544c1 |
tcg_target_call_iarg_regs[2]);
|
|
|
5544c1 |
@@ -1255,7 +1232,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
tcg_target_call_iarg_regs[0]);
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
|
|
|
5544c1 |
TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
tcg_out_call(s, qemu_st_helpers[opc]);
|
|
|
5544c1 |
|
|
|
5544c1 |
/* label2: */
|
|
|
5544c1 |
diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
|
|
|
5544c1 |
index d4bf6fe..01ef960 100644
|
|
|
5544c1 |
--- a/tcg/hppa/tcg-target.h
|
|
|
5544c1 |
+++ b/tcg/hppa/tcg-target.h
|
|
|
5544c1 |
@@ -104,7 +104,6 @@ typedef enum {
|
|
|
5544c1 |
|
|
|
5544c1 |
#define TCG_TARGET_HAS_GUEST_BASE
|
|
|
5544c1 |
|
|
|
5544c1 |
-/* Note: must be synced with dyngen-exec.h */
|
|
|
5544c1 |
#define TCG_AREG0 TCG_REG_R17
|
|
|
5544c1 |
|
|
|
5544c1 |
|
|
|
5544c1 |
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
|
|
|
5544c1 |
index da17bba..34c2df8 100644
|
|
|
5544c1 |
--- a/tcg/i386/tcg-target.c
|
|
|
5544c1 |
+++ b/tcg/i386/tcg-target.c
|
|
|
5544c1 |
@@ -183,9 +183,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
tcg_regset_set32(ct->u.regs, 0, 0xffff);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
} else {
|
|
|
5544c1 |
tcg_regset_set32(ct->u.regs, 0, 0xff);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
|
|
|
5544c1 |
@@ -965,7 +963,6 @@ static void tcg_out_jmp(TCGContext *s, tcg_target_long dest)
|
|
|
5544c1 |
|
|
|
5544c1 |
#include "../../softmmu_defs.h"
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
|
|
|
5544c1 |
int mmu_idx) */
|
|
|
5544c1 |
static const void *qemu_ld_helpers[4] = {
|
|
|
5544c1 |
@@ -983,25 +980,6 @@ static const void *qemu_st_helpers[4] = {
|
|
|
5544c1 |
helper_stl_mmu,
|
|
|
5544c1 |
helper_stq_mmu,
|
|
|
5544c1 |
};
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
|
|
|
5544c1 |
- mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_ld_helpers[4] = {
|
|
|
5544c1 |
- __ldb_mmu,
|
|
|
5544c1 |
- __ldw_mmu,
|
|
|
5544c1 |
- __ldl_mmu,
|
|
|
5544c1 |
- __ldq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
|
|
|
5544c1 |
- int mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_st_helpers[4] = {
|
|
|
5544c1 |
- __stb_mmu,
|
|
|
5544c1 |
- __stw_mmu,
|
|
|
5544c1 |
- __stl_mmu,
|
|
|
5544c1 |
- __stq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Perform the TLB load and compare.
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -1220,16 +1198,13 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
|
|
|
5544c1 |
}
|
|
|
5544c1 |
tcg_out_push(s, args[addrlo_idx]);
|
|
|
5544c1 |
stack_adjust += 4;
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_out_push(s, TCG_AREG0);
|
|
|
5544c1 |
stack_adjust += 4;
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
#else
|
|
|
5544c1 |
/* The first argument is already loaded with addrlo. */
|
|
|
5544c1 |
arg_idx = 1;
|
|
|
5544c1 |
tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[arg_idx],
|
|
|
5544c1 |
mem_index);
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* XXX/FIXME: suboptimal */
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
|
|
|
5544c1 |
tcg_target_call_iarg_regs[2]);
|
|
|
5544c1 |
@@ -1240,7 +1215,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
|
|
|
5544c1 |
TCG_AREG0);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
tcg_out_calli(s, (tcg_target_long)qemu_ld_helpers[s_bits]);
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -1436,16 +1410,13 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
|
|
|
5544c1 |
}
|
|
|
5544c1 |
tcg_out_push(s, args[addrlo_idx]);
|
|
|
5544c1 |
stack_adjust += 4;
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_out_push(s, TCG_AREG0);
|
|
|
5544c1 |
stack_adjust += 4;
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
#else
|
|
|
5544c1 |
tcg_out_mov(s, (opc == 3 ? TCG_TYPE_I64 : TCG_TYPE_I32),
|
|
|
5544c1 |
tcg_target_call_iarg_regs[1], data_reg);
|
|
|
5544c1 |
tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], mem_index);
|
|
|
5544c1 |
stack_adjust = 0;
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* XXX/FIXME: suboptimal */
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
|
|
|
5544c1 |
tcg_target_call_iarg_regs[2]);
|
|
|
5544c1 |
@@ -1456,7 +1427,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
|
|
|
5544c1 |
TCG_AREG0);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
tcg_out_calli(s, (tcg_target_long)qemu_st_helpers[s_bits]);
|
|
|
5544c1 |
|
|
|
5544c1 |
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
|
|
|
5544c1 |
index c3cfe05..8be42f3 100644
|
|
|
5544c1 |
--- a/tcg/i386/tcg-target.h
|
|
|
5544c1 |
+++ b/tcg/i386/tcg-target.h
|
|
|
5544c1 |
@@ -116,7 +116,6 @@ typedef enum {
|
|
|
5544c1 |
|
|
|
5544c1 |
#define TCG_TARGET_HAS_GUEST_BASE
|
|
|
5544c1 |
|
|
|
5544c1 |
-/* Note: must be synced with dyngen-exec.h */
|
|
|
5544c1 |
#if TCG_TARGET_REG_BITS == 64
|
|
|
5544c1 |
# define TCG_AREG0 TCG_REG_R14
|
|
|
5544c1 |
#else
|
|
|
5544c1 |
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
|
|
|
5544c1 |
index dc588db..1745038 100644
|
|
|
5544c1 |
--- a/tcg/ia64/tcg-target.c
|
|
|
5544c1 |
+++ b/tcg/ia64/tcg-target.c
|
|
|
5544c1 |
@@ -1452,7 +1452,6 @@ static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
|
|
|
5544c1 |
TCG_REG_P7, TCG_REG_R3, TCG_REG_R57));
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
|
|
|
5544c1 |
int mmu_idx) */
|
|
|
5544c1 |
static const void * const qemu_ld_helpers[4] = {
|
|
|
5544c1 |
@@ -1461,16 +1460,6 @@ static const void * const qemu_ld_helpers[4] = {
|
|
|
5544c1 |
helper_ldl_mmu,
|
|
|
5544c1 |
helper_ldq_mmu,
|
|
|
5544c1 |
};
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
|
|
|
5544c1 |
- mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_ld_helpers[4] = {
|
|
|
5544c1 |
- __ldb_mmu,
|
|
|
5544c1 |
- __ldw_mmu,
|
|
|
5544c1 |
- __ldl_mmu,
|
|
|
5544c1 |
- __ldq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
@@ -1530,7 +1519,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
|
|
|
5544c1 |
tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
|
|
|
5544c1 |
}
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* XXX/FIXME: suboptimal */
|
|
|
5544c1 |
tcg_out_bundle(s, mII,
|
|
|
5544c1 |
tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
|
|
|
5544c1 |
@@ -1539,7 +1527,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
TCG_REG_R57, 0, TCG_REG_R56),
|
|
|
5544c1 |
tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
|
|
|
5544c1 |
TCG_REG_R56, 0, TCG_AREG0));
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
if (!bswap || s_bits == 0) {
|
|
|
5544c1 |
tcg_out_bundle(s, miB,
|
|
|
5544c1 |
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
|
|
|
5544c1 |
@@ -1570,7 +1557,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
|
|
|
5544c1 |
uintxx_t val, int mmu_idx) */
|
|
|
5544c1 |
static const void * const qemu_st_helpers[4] = {
|
|
|
5544c1 |
@@ -1579,16 +1565,6 @@ static const void * const qemu_st_helpers[4] = {
|
|
|
5544c1 |
helper_stl_mmu,
|
|
|
5544c1 |
helper_stq_mmu,
|
|
|
5544c1 |
};
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
|
|
|
5544c1 |
- int mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_st_helpers[4] = {
|
|
|
5544c1 |
- __stb_mmu,
|
|
|
5544c1 |
- __stw_mmu,
|
|
|
5544c1 |
- __stl_mmu,
|
|
|
5544c1 |
- __stq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
@@ -1658,7 +1634,6 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
data_reg = TCG_REG_R2;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* XXX/FIXME: suboptimal */
|
|
|
5544c1 |
tcg_out_bundle(s, mII,
|
|
|
5544c1 |
tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
|
|
|
5544c1 |
@@ -1674,15 +1649,6 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
TCG_REG_R56, 0, TCG_AREG0),
|
|
|
5544c1 |
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
|
|
|
5544c1 |
TCG_REG_B0, TCG_REG_B6));
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
- tcg_out_bundle(s, miB,
|
|
|
5544c1 |
- tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
|
|
|
5544c1 |
- data_reg, TCG_REG_R3),
|
|
|
5544c1 |
- tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
|
|
|
5544c1 |
- mem_index, TCG_REG_R0),
|
|
|
5544c1 |
- tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
|
|
|
5544c1 |
- TCG_REG_B0, TCG_REG_B6));
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
#else /* !CONFIG_SOFTMMU */
|
|
|
5544c1 |
diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
|
|
|
5544c1 |
index 0631b9f..c22962a 100644
|
|
|
5544c1 |
--- a/tcg/ia64/tcg-target.h
|
|
|
5544c1 |
+++ b/tcg/ia64/tcg-target.h
|
|
|
5544c1 |
@@ -140,7 +140,6 @@ typedef enum {
|
|
|
5544c1 |
#define TCG_TARGET_HAS_not_i32 0 /* xor r1, -1, r3 */
|
|
|
5544c1 |
#define TCG_TARGET_HAS_not_i64 0 /* xor r1, -1, r3 */
|
|
|
5544c1 |
|
|
|
5544c1 |
-/* Note: must be synced with dyngen-exec.h */
|
|
|
5544c1 |
#define TCG_AREG0 TCG_REG_R7
|
|
|
5544c1 |
|
|
|
5544c1 |
/* Guest base is supported */
|
|
|
5544c1 |
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
|
|
|
5544c1 |
index 1006e28..74db83d 100644
|
|
|
5544c1 |
--- a/tcg/mips/tcg-target.c
|
|
|
5544c1 |
+++ b/tcg/mips/tcg-target.c
|
|
|
5544c1 |
@@ -217,7 +217,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
tcg_regset_set(ct->u.regs, 0xffffffff);
|
|
|
5544c1 |
#if defined(CONFIG_SOFTMMU)
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
|
|
|
5544c1 |
-# if defined(CONFIG_TCG_PASS_AREG0) && (TARGET_LONG_BITS == 64)
|
|
|
5544c1 |
+# if (TARGET_LONG_BITS == 64)
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
|
|
|
5544c1 |
# endif
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
@@ -227,12 +227,11 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
tcg_regset_set(ct->u.regs, 0xffffffff);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
|
|
|
5544c1 |
#if defined(CONFIG_SOFTMMU)
|
|
|
5544c1 |
-# if (defined(CONFIG_TCG_PASS_AREG0) && TARGET_LONG_BITS == 32) || \
|
|
|
5544c1 |
- (!defined(CONFIG_TCG_PASS_AREG0) && TARGET_LONG_BITS == 64)
|
|
|
5544c1 |
+# if (TARGET_LONG_BITS == 32)
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
|
|
|
5544c1 |
# endif
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
|
|
|
5544c1 |
-# if defined(CONFIG_TCG_PASS_AREG0) && TARGET_LONG_BITS == 64
|
|
|
5544c1 |
+# if TARGET_LONG_BITS == 64
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
|
|
|
5544c1 |
# endif
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
@@ -821,7 +820,6 @@ static void tcg_out_setcond2(TCGContext *s, TCGCond cond, int ret,
|
|
|
5544c1 |
|
|
|
5544c1 |
#include "../../softmmu_defs.h"
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
|
|
|
5544c1 |
int mmu_idx) */
|
|
|
5544c1 |
static const void * const qemu_ld_helpers[4] = {
|
|
|
5544c1 |
@@ -839,25 +837,6 @@ static const void * const qemu_st_helpers[4] = {
|
|
|
5544c1 |
helper_stl_mmu,
|
|
|
5544c1 |
helper_stq_mmu,
|
|
|
5544c1 |
};
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
|
|
|
5544c1 |
- mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_ld_helpers[4] = {
|
|
|
5544c1 |
- __ldb_mmu,
|
|
|
5544c1 |
- __ldw_mmu,
|
|
|
5544c1 |
- __ldl_mmu,
|
|
|
5544c1 |
- __ldq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
|
|
|
5544c1 |
- int mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_st_helpers[4] = {
|
|
|
5544c1 |
- __stb_mmu,
|
|
|
5544c1 |
- __stw_mmu,
|
|
|
5544c1 |
- __stl_mmu,
|
|
|
5544c1 |
- __stq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
|
|
|
5544c1 |
@@ -942,9 +921,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
|
|
|
5544c1 |
|
|
|
5544c1 |
/* slow path */
|
|
|
5544c1 |
arg_num = 0;
|
|
|
5544c1 |
-# ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_out_call_iarg_reg32(s, &arg_num, TCG_AREG0);
|
|
|
5544c1 |
-# endif
|
|
|
5544c1 |
# if TARGET_LONG_BITS == 64
|
|
|
5544c1 |
tcg_out_call_iarg_reg64(s, &arg_num, addr_regl, addr_regh);
|
|
|
5544c1 |
# else
|
|
|
5544c1 |
@@ -1127,9 +1104,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
|
|
|
5544c1 |
|
|
|
5544c1 |
/* slow path */
|
|
|
5544c1 |
arg_num = 0;
|
|
|
5544c1 |
-# ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_out_call_iarg_reg32(s, &arg_num, TCG_AREG0);
|
|
|
5544c1 |
-# endif
|
|
|
5544c1 |
# if TARGET_LONG_BITS == 64
|
|
|
5544c1 |
tcg_out_call_iarg_reg64(s, &arg_num, addr_regl, addr_regh);
|
|
|
5544c1 |
# else
|
|
|
5544c1 |
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
|
|
|
5544c1 |
index d3c804d..1c61931 100644
|
|
|
5544c1 |
--- a/tcg/mips/tcg-target.h
|
|
|
5544c1 |
+++ b/tcg/mips/tcg-target.h
|
|
|
5544c1 |
@@ -96,7 +96,6 @@ typedef enum {
|
|
|
5544c1 |
#define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
|
|
|
5544c1 |
#define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
|
|
|
5544c1 |
|
|
|
5544c1 |
-/* Note: must be synced with dyngen-exec.h */
|
|
|
5544c1 |
#define TCG_AREG0 TCG_REG_S0
|
|
|
5544c1 |
|
|
|
5544c1 |
/* guest base is supported */
|
|
|
5544c1 |
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
|
|
|
5544c1 |
index 0cff181..26c4b33 100644
|
|
|
5544c1 |
--- a/tcg/ppc/tcg-target.c
|
|
|
5544c1 |
+++ b/tcg/ppc/tcg-target.c
|
|
|
5544c1 |
@@ -248,7 +248,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
|
|
|
5544c1 |
#if TARGET_LONG_BITS == 64
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
|
|
|
5544c1 |
@@ -256,11 +255,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
-#else /* !AREG0 */
|
|
|
5544c1 |
-#if TARGET_LONG_BITS == 64
|
|
|
5544c1 |
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case 'K': /* qemu_st[8..32] constraint */
|
|
|
5544c1 |
ct->ct |= TCG_CT_REG;
|
|
|
5544c1 |
@@ -268,7 +262,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
|
|
|
5544c1 |
#if TARGET_LONG_BITS == 64
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
|
|
|
5544c1 |
@@ -276,11 +269,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
-#else /* !AREG0 */
|
|
|
5544c1 |
-#if TARGET_LONG_BITS == 64
|
|
|
5544c1 |
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case 'M': /* qemu_st64 constraint */
|
|
|
5544c1 |
ct->ct |= TCG_CT_REG;
|
|
|
5544c1 |
@@ -290,12 +278,10 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
|
|
|
5544c1 |
-#if defined(CONFIG_TCG_PASS_AREG0)
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
|
|
|
5544c1 |
#ifdef TCG_TARGET_CALL_ALIGN_ARGS
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R9);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
#else
|
|
|
5544c1 |
case 'L':
|
|
|
5544c1 |
@@ -541,7 +527,6 @@ static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
|
|
|
5544c1 |
|
|
|
5544c1 |
#include "../../softmmu_defs.h"
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
|
|
|
5544c1 |
int mmu_idx) */
|
|
|
5544c1 |
static const void * const qemu_ld_helpers[4] = {
|
|
|
5544c1 |
@@ -559,25 +544,6 @@ static const void * const qemu_st_helpers[4] = {
|
|
|
5544c1 |
helper_stl_mmu,
|
|
|
5544c1 |
helper_stq_mmu,
|
|
|
5544c1 |
};
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
|
|
|
5544c1 |
- mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_ld_helpers[4] = {
|
|
|
5544c1 |
- __ldb_mmu,
|
|
|
5544c1 |
- __ldw_mmu,
|
|
|
5544c1 |
- __ldl_mmu,
|
|
|
5544c1 |
- __ldq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
|
|
|
5544c1 |
- mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_st_helpers[4] = {
|
|
|
5544c1 |
- __stb_mmu,
|
|
|
5544c1 |
- __stw_mmu,
|
|
|
5544c1 |
- __stl_mmu,
|
|
|
5544c1 |
- __stq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
@@ -647,9 +613,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
|
|
|
5544c1 |
/* slow path */
|
|
|
5544c1 |
ir = 3;
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
#if TARGET_LONG_BITS == 32
|
|
|
5544c1 |
tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
|
|
|
5544c1 |
#else
|
|
|
5544c1 |
@@ -849,9 +813,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
|
|
|
5544c1 |
/* slow path */
|
|
|
5544c1 |
ir = 3;
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
#if TARGET_LONG_BITS == 32
|
|
|
5544c1 |
tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
|
|
|
5544c1 |
#else
|
|
|
5544c1 |
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
|
|
|
5544c1 |
index 27a0ae8..337cd41 100644
|
|
|
5544c1 |
--- a/tcg/ppc64/tcg-target.c
|
|
|
5544c1 |
+++ b/tcg/ppc64/tcg-target.c
|
|
|
5544c1 |
@@ -235,10 +235,8 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
|
|
|
5544c1 |
#ifdef CONFIG_SOFTMMU
|
|
|
5544c1 |
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case 'S': /* qemu_st constraint */
|
|
|
5544c1 |
ct->ct |= TCG_CT_REG;
|
|
|
5544c1 |
@@ -247,10 +245,8 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
#ifdef CONFIG_SOFTMMU
|
|
|
5544c1 |
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
|
|
|
5544c1 |
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6);
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case 'Z':
|
|
|
5544c1 |
ct->ct |= TCG_CT_CONST_U32;
|
|
|
5544c1 |
@@ -558,7 +554,6 @@ static void tcg_out_ldsta (TCGContext *s, int ret, int addr,
|
|
|
5544c1 |
|
|
|
5544c1 |
#include "../../softmmu_defs.h"
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
|
|
|
5544c1 |
int mmu_idx) */
|
|
|
5544c1 |
static const void * const qemu_ld_helpers[4] = {
|
|
|
5544c1 |
@@ -576,25 +571,6 @@ static const void * const qemu_st_helpers[4] = {
|
|
|
5544c1 |
helper_stl_mmu,
|
|
|
5544c1 |
helper_stq_mmu,
|
|
|
5544c1 |
};
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
|
|
|
5544c1 |
- mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_ld_helpers[4] = {
|
|
|
5544c1 |
- __ldb_mmu,
|
|
|
5544c1 |
- __ldw_mmu,
|
|
|
5544c1 |
- __ldl_mmu,
|
|
|
5544c1 |
- __ldq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
|
|
|
5544c1 |
- int mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_st_helpers[4] = {
|
|
|
5544c1 |
- __stb_mmu,
|
|
|
5544c1 |
- __stw_mmu,
|
|
|
5544c1 |
- __stl_mmu,
|
|
|
5544c1 |
- __stq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2,
|
|
|
5544c1 |
int addr_reg, int s_bits, int offset)
|
|
|
5544c1 |
@@ -676,9 +652,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
|
|
|
5544c1 |
/* slow path */
|
|
|
5544c1 |
ir = 3;
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg);
|
|
|
5544c1 |
tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index);
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -827,9 +801,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
|
|
|
5544c1 |
|
|
|
5544c1 |
/* slow path */
|
|
|
5544c1 |
ir = 3;
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_out_mov (s, TCG_TYPE_I64, ir++, TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
tcg_out_mov (s, TCG_TYPE_I64, ir++, addr_reg);
|
|
|
5544c1 |
tcg_out_rld (s, RLDICL, ir++, data_reg, 0, 64 - (1 << (3 + opc)));
|
|
|
5544c1 |
tcg_out_movi (s, TCG_TYPE_I64, ir++, mem_index);
|
|
|
5544c1 |
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
|
|
|
5544c1 |
index 99b5339..aac11d9 100644
|
|
|
5544c1 |
--- a/tcg/s390/tcg-target.c
|
|
|
5544c1 |
+++ b/tcg/s390/tcg-target.c
|
|
|
5544c1 |
@@ -301,7 +301,6 @@ static const uint8_t tcg_cond_to_ltr_cond[10] = {
|
|
|
5544c1 |
|
|
|
5544c1 |
#include "../../softmmu_defs.h"
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
|
|
|
5544c1 |
int mmu_idx) */
|
|
|
5544c1 |
static const void * const qemu_ld_helpers[4] = {
|
|
|
5544c1 |
@@ -319,25 +318,6 @@ static const void * const qemu_st_helpers[4] = {
|
|
|
5544c1 |
helper_stl_mmu,
|
|
|
5544c1 |
helper_stq_mmu,
|
|
|
5544c1 |
};
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
|
|
|
5544c1 |
- mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_ld_helpers[4] = {
|
|
|
5544c1 |
- __ldb_mmu,
|
|
|
5544c1 |
- __ldw_mmu,
|
|
|
5544c1 |
- __ldl_mmu,
|
|
|
5544c1 |
- __ldq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
|
|
|
5544c1 |
- int mmu_idx) */
|
|
|
5544c1 |
-static void *qemu_st_helpers[4] = {
|
|
|
5544c1 |
- __stb_mmu,
|
|
|
5544c1 |
- __stw_mmu,
|
|
|
5544c1 |
- __stl_mmu,
|
|
|
5544c1 |
- __stq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
static uint8_t *tb_ret_addr;
|
|
|
5544c1 |
@@ -1507,7 +1487,6 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
|
|
|
5544c1 |
tcg_abort();
|
|
|
5544c1 |
}
|
|
|
5544c1 |
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, mem_index);
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* XXX/FIXME: suboptimal */
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3],
|
|
|
5544c1 |
tcg_target_call_iarg_regs[2]);
|
|
|
5544c1 |
@@ -1517,11 +1496,9 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
|
|
|
5544c1 |
tcg_target_call_iarg_regs[0]);
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
|
|
|
5544c1 |
TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
tgen_calli(s, (tcg_target_ulong)qemu_st_helpers[s_bits]);
|
|
|
5544c1 |
} else {
|
|
|
5544c1 |
tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* XXX/FIXME: suboptimal */
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2],
|
|
|
5544c1 |
tcg_target_call_iarg_regs[1]);
|
|
|
5544c1 |
@@ -1529,7 +1506,6 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg,
|
|
|
5544c1 |
tcg_target_call_iarg_regs[0]);
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0],
|
|
|
5544c1 |
TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
tgen_calli(s, (tcg_target_ulong)qemu_ld_helpers[s_bits]);
|
|
|
5544c1 |
|
|
|
5544c1 |
/* sign extension */
|
|
|
5544c1 |
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
|
|
|
5544c1 |
index d12f90b..4f7dfab 100644
|
|
|
5544c1 |
--- a/tcg/s390/tcg-target.h
|
|
|
5544c1 |
+++ b/tcg/s390/tcg-target.h
|
|
|
5544c1 |
@@ -96,7 +96,6 @@ typedef enum TCGReg {
|
|
|
5544c1 |
#define TCG_TARGET_EXTEND_ARGS 1
|
|
|
5544c1 |
|
|
|
5544c1 |
enum {
|
|
|
5544c1 |
- /* Note: must be synced with dyngen-exec.h */
|
|
|
5544c1 |
TCG_AREG0 = TCG_REG_R10,
|
|
|
5544c1 |
};
|
|
|
5544c1 |
|
|
|
5544c1 |
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
|
|
|
5544c1 |
index 247a278..baed3b4 100644
|
|
|
5544c1 |
--- a/tcg/sparc/tcg-target.c
|
|
|
5544c1 |
+++ b/tcg/sparc/tcg-target.c
|
|
|
5544c1 |
@@ -59,11 +59,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
|
|
|
5544c1 |
};
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
#define ARG_OFFSET 1
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-#define ARG_OFFSET 0
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
static const int tcg_target_reg_alloc_order[] = {
|
|
|
5544c1 |
TCG_REG_L0,
|
|
|
5544c1 |
@@ -161,9 +157,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O3);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case 'I':
|
|
|
5544c1 |
ct->ct |= TCG_CT_CONST_S11;
|
|
|
5544c1 |
@@ -715,7 +709,6 @@ static void tcg_target_qemu_prologue(TCGContext *s)
|
|
|
5544c1 |
|
|
|
5544c1 |
#include "../../softmmu_defs.h"
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
|
|
|
5544c1 |
int mmu_idx) */
|
|
|
5544c1 |
static const void * const qemu_ld_helpers[4] = {
|
|
|
5544c1 |
@@ -733,25 +726,6 @@ static const void * const qemu_st_helpers[4] = {
|
|
|
5544c1 |
helper_stl_mmu,
|
|
|
5544c1 |
helper_stq_mmu,
|
|
|
5544c1 |
};
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-/* legacy helper signature: __ld_mmu(target_ulong addr, int
|
|
|
5544c1 |
- mmu_idx) */
|
|
|
5544c1 |
-static const void * const qemu_ld_helpers[4] = {
|
|
|
5544c1 |
- __ldb_mmu,
|
|
|
5544c1 |
- __ldw_mmu,
|
|
|
5544c1 |
- __ldl_mmu,
|
|
|
5544c1 |
- __ldq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
|
|
|
5544c1 |
- int mmu_idx) */
|
|
|
5544c1 |
-static const void * const qemu_st_helpers[4] = {
|
|
|
5544c1 |
- __stb_mmu,
|
|
|
5544c1 |
- __stw_mmu,
|
|
|
5544c1 |
- __stl_mmu,
|
|
|
5544c1 |
- __stq_mmu,
|
|
|
5544c1 |
-};
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
#if TARGET_LONG_BITS == 32
|
|
|
5544c1 |
@@ -834,7 +808,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
|
|
|
5544c1 |
|
|
|
5544c1 |
/* mov */
|
|
|
5544c1 |
tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* XXX/FIXME: suboptimal */
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
|
|
|
5544c1 |
tcg_target_call_iarg_regs[2]);
|
|
|
5544c1 |
@@ -844,7 +817,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
|
|
|
5544c1 |
tcg_target_call_iarg_regs[0]);
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
|
|
|
5544c1 |
TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
/* XXX: move that code at the end of the TB */
|
|
|
5544c1 |
/* qemu_ld_helper[s_bits](arg0, arg1) */
|
|
|
5544c1 |
@@ -1061,7 +1033,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
|
|
|
5544c1 |
/* mov */
|
|
|
5544c1 |
tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
/* XXX/FIXME: suboptimal */
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3],
|
|
|
5544c1 |
tcg_target_call_iarg_regs[2]);
|
|
|
5544c1 |
@@ -1071,7 +1042,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
|
|
|
5544c1 |
tcg_target_call_iarg_regs[0]);
|
|
|
5544c1 |
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0],
|
|
|
5544c1 |
TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
/* XXX: move that code at the end of the TB */
|
|
|
5544c1 |
/* qemu_st_helper[s_bits](arg0, arg1, arg2) */
|
|
|
5544c1 |
tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
|
|
|
5544c1 |
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
|
|
|
5544c1 |
index ee2274d..0ea87be 100644
|
|
|
5544c1 |
--- a/tcg/sparc/tcg-target.h
|
|
|
5544c1 |
+++ b/tcg/sparc/tcg-target.h
|
|
|
5544c1 |
@@ -125,7 +125,6 @@ typedef enum {
|
|
|
5544c1 |
#define TCG_TARGET_HAS_deposit_i64 0
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
-/* Note: must be synced with dyngen-exec.h */
|
|
|
5544c1 |
#ifdef CONFIG_SOLARIS
|
|
|
5544c1 |
#define TCG_AREG0 TCG_REG_G2
|
|
|
5544c1 |
#elif defined(__sparc_v9__)
|
|
|
5544c1 |
diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c
|
|
|
5544c1 |
index ef8580f..003244c 100644
|
|
|
5544c1 |
--- a/tcg/tci/tcg-target.c
|
|
|
5544c1 |
+++ b/tcg/tci/tcg-target.c
|
|
|
5544c1 |
@@ -798,9 +798,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
|
|
|
5544c1 |
case INDEX_op_qemu_st8:
|
|
|
5544c1 |
case INDEX_op_qemu_st16:
|
|
|
5544c1 |
case INDEX_op_qemu_st32:
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_out_r(s, TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
tcg_out_r(s, *args++);
|
|
|
5544c1 |
tcg_out_r(s, *args++);
|
|
|
5544c1 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
|
|
5544c1 |
@@ -811,9 +809,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case INDEX_op_qemu_st64:
|
|
|
5544c1 |
-#ifdef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
tcg_out_r(s, TCG_AREG0);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
tcg_out_r(s, *args++);
|
|
|
5544c1 |
#if TCG_TARGET_REG_BITS == 32
|
|
|
5544c1 |
tcg_out_r(s, *args++);
|
|
|
5544c1 |
diff --git a/tci.c b/tci.c
|
|
|
5544c1 |
index c79350d..ce8a988 100644
|
|
|
5544c1 |
--- a/tci.c
|
|
|
5544c1 |
+++ b/tci.c
|
|
|
5544c1 |
@@ -25,7 +25,6 @@
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
#include "qemu-common.h"
|
|
|
5544c1 |
-#include "dyngen-exec.h" /* env */
|
|
|
5544c1 |
#include "exec-all.h" /* MAX_OPC_PARAM_IARGS */
|
|
|
5544c1 |
#include "tcg-op.h"
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -63,17 +62,6 @@ uintptr_t tci_tb_ptr;
|
|
|
5544c1 |
|
|
|
5544c1 |
static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS];
|
|
|
5544c1 |
|
|
|
5544c1 |
-#if !defined(CONFIG_TCG_PASS_AREG0)
|
|
|
5544c1 |
-# define helper_ldb_mmu(env, addr, mmu_idx) __ldb_mmu(addr, mmu_idx)
|
|
|
5544c1 |
-# define helper_ldw_mmu(env, addr, mmu_idx) __ldw_mmu(addr, mmu_idx)
|
|
|
5544c1 |
-# define helper_ldl_mmu(env, addr, mmu_idx) __ldl_mmu(addr, mmu_idx)
|
|
|
5544c1 |
-# define helper_ldq_mmu(env, addr, mmu_idx) __ldq_mmu(addr, mmu_idx)
|
|
|
5544c1 |
-# define helper_stb_mmu(env, addr, val, mmu_idx) __stb_mmu(addr, val, mmu_idx)
|
|
|
5544c1 |
-# define helper_stw_mmu(env, addr, val, mmu_idx) __stw_mmu(addr, val, mmu_idx)
|
|
|
5544c1 |
-# define helper_stl_mmu(env, addr, val, mmu_idx) __stl_mmu(addr, val, mmu_idx)
|
|
|
5544c1 |
-# define helper_stq_mmu(env, addr, val, mmu_idx) __stq_mmu(addr, val, mmu_idx)
|
|
|
5544c1 |
-#endif /* !CONFIG_TCG_PASS_AREG0 */
|
|
|
5544c1 |
-
|
|
|
5544c1 |
static tcg_target_ulong tci_read_reg(TCGReg index)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
assert(index < ARRAY_SIZE(tci_reg));
|
|
|
5544c1 |
diff --git a/user-exec.c b/user-exec.c
|
|
|
5544c1 |
index b9ea9dd..ef9b172 100644
|
|
|
5544c1 |
--- a/user-exec.c
|
|
|
5544c1 |
+++ b/user-exec.c
|
|
|
5544c1 |
@@ -18,9 +18,6 @@
|
|
|
5544c1 |
*/
|
|
|
5544c1 |
#include "config.h"
|
|
|
5544c1 |
#include "cpu.h"
|
|
|
5544c1 |
-#ifndef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
-#include "dyngen-exec.h"
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
#include "disas.h"
|
|
|
5544c1 |
#include "tcg.h"
|
|
|
5544c1 |
|
|
|
5544c1 |
@@ -60,12 +57,6 @@ void cpu_resume_from_signal(CPUArchState *env1, void *puc)
|
|
|
5544c1 |
struct sigcontext *uc = puc;
|
|
|
5544c1 |
#endif
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifndef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
- env = env1;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- /* XXX: restore cpu registers saved in host registers */
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
-
|
|
|
5544c1 |
if (puc) {
|
|
|
5544c1 |
/* XXX: use siglongjmp ? */
|
|
|
5544c1 |
#ifdef __linux__
|
|
|
5544c1 |
@@ -93,11 +84,6 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
|
|
|
5544c1 |
TranslationBlock *tb;
|
|
|
5544c1 |
int ret;
|
|
|
5544c1 |
|
|
|
5544c1 |
-#ifndef CONFIG_TCG_PASS_AREG0
|
|
|
5544c1 |
- if (cpu_single_env) {
|
|
|
5544c1 |
- env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
#if defined(DEBUG_SIGNAL)
|
|
|
5544c1 |
qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
|
5544c1 |
pc, address, is_write, *(unsigned long *)old_set);
|
|
|
5544c1 |
--
|
|
|
5544c1 |
1.7.12.1
|
|
|
5544c1 |
|