From d8503917ec9ba86829387f05db7da2eb6fa8123f Mon Sep 17 00:00:00 2001

From: Blue Swirl <blauwirbel@gmail.com>

Date: Sat, 8 Sep 2012 11:15:37 +0000

Subject: [PATCH] target-s390x: avoid cpu_single_env

Pass around CPUState instead of using global cpu_single_env.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>

---

 target-s390x/translate.c | 356 ++++++++++++++++++++++++-----------------------

 1 file changed, 183 insertions(+), 173 deletions(-)

diff --git a/target-s390x/translate.c b/target-s390x/translate.c

index 66119cd..3214783 100644

--- a/target-s390x/translate.c

+++ b/target-s390x/translate.c

@@ -274,21 +274,21 @@ static inline void potential_page_fault(DisasContext *s)

 #endif

 }

-static inline uint64_t ld_code2(uint64_t pc)

+static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)

 {

-    return (uint64_t)cpu_lduw_code(cpu_single_env, pc);

+    return (uint64_t)cpu_lduw_code(env, pc);

 }

-static inline uint64_t ld_code4(uint64_t pc)

+static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)

 {

-    return (uint64_t)cpu_ldl_code(cpu_single_env, pc);

+    return (uint64_t)cpu_ldl_code(env, pc);

 }

-static inline uint64_t ld_code6(uint64_t pc)

+static inline uint64_t ld_code6(CPUS390XState *env, uint64_t pc)

 {

     uint64_t opc;

-    opc = (uint64_t)cpu_lduw_code(cpu_single_env, pc) << 32;

-    opc |= (uint64_t)(uint32_t)cpu_ldl_code(cpu_single_env, pc + 2);

+    opc = (uint64_t)cpu_lduw_code(env, pc) << 32;

+    opc |= (uint64_t)(uint32_t)cpu_ldl_code(env, pc + 2);

     return opc;

 }

@@ -319,7 +319,7 @@ static inline void gen_debug(DisasContext *s)

 #ifdef CONFIG_USER_ONLY

-static void gen_illegal_opcode(DisasContext *s, int ilc)

+static void gen_illegal_opcode(CPUS390XState *env, DisasContext *s, int ilc)

 {

     TCGv_i32 tmp = tcg_const_i32(EXCP_SPEC);

     update_psw_addr(s);

@@ -331,20 +331,20 @@ static void gen_illegal_opcode(DisasContext *s, int ilc)

 #else /* CONFIG_USER_ONLY */

-static void debug_print_inst(DisasContext *s, int ilc)

+static void debug_print_inst(CPUS390XState *env, DisasContext *s, int ilc)

 {

 #ifdef DEBUG_ILLEGAL_INSTRUCTIONS

     uint64_t inst = 0;

     switch (ilc & 3) {

     case 1:

-        inst = ld_code2(s->pc);

+        inst = ld_code2(env, s->pc);

         break;

     case 2:

-        inst = ld_code4(s->pc);

+        inst = ld_code4(env, s->pc);

         break;

     case 3:

-        inst = ld_code6(s->pc);

+        inst = ld_code6(env, s->pc);

         break;

     }

@@ -353,11 +353,12 @@ static void debug_print_inst(DisasContext *s, int ilc)

 #endif

 }

-static void gen_program_exception(DisasContext *s, int ilc, int code)

+static void gen_program_exception(CPUS390XState *env, DisasContext *s, int ilc,

+                                  int code)

 {

     TCGv_i32 tmp;

-    debug_print_inst(s, ilc);

+    debug_print_inst(env, s, ilc);

     /* remember what pgm exeption this was */

     tmp = tcg_const_i32(code);

@@ -385,20 +386,21 @@ static void gen_program_exception(DisasContext *s, int ilc, int code)

 }

-static void gen_illegal_opcode(DisasContext *s, int ilc)

+static void gen_illegal_opcode(CPUS390XState *env, DisasContext *s, int ilc)

 {

-    gen_program_exception(s, ilc, PGM_SPECIFICATION);

+    gen_program_exception(env, s, ilc, PGM_SPECIFICATION);

 }

-static void gen_privileged_exception(DisasContext *s, int ilc)

+static void gen_privileged_exception(CPUS390XState *env, DisasContext *s,

+                                     int ilc)

 {

-    gen_program_exception(s, ilc, PGM_PRIVILEGED);

+    gen_program_exception(env, s, ilc, PGM_PRIVILEGED);

 }

-static void check_privileged(DisasContext *s, int ilc)

+static void check_privileged(CPUS390XState *env, DisasContext *s, int ilc)

 {

     if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {

-        gen_privileged_exception(s, ilc);

+        gen_privileged_exception(env, s, ilc);

     }

 }

@@ -1460,7 +1462,8 @@ static void gen_op_clc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2)

     set_cc_static(s);

 }

-static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2)

+static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1,

+                     int x2, int b2, int d2)

 {

     TCGv_i64 addr, tmp, tmp2, tmp3, tmp4;

     TCGv_i32 tmp32_1, tmp32_2, tmp32_3;

@@ -1925,14 +1928,14 @@ static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2)

         break;

     default:

         LOG_DISAS("illegal e3 operation 0x%x\n", op);

-        gen_illegal_opcode(s, 3);

+        gen_illegal_opcode(env, s, 3);

         break;

     }

     tcg_temp_free_i64(addr);

 }

 #ifndef CONFIG_USER_ONLY

-static void disas_e5(DisasContext* s, uint64_t insn)

+static void disas_e5(CPUS390XState *env, DisasContext* s, uint64_t insn)

 {

     TCGv_i64 tmp, tmp2;

     int op = (insn >> 32) & 0xff;

@@ -1950,7 +1953,7 @@ static void disas_e5(DisasContext* s, uint64_t insn)

         break;

     default:

         LOG_DISAS("illegal e5 operation 0x%x\n", op);

-        gen_illegal_opcode(s, 3);

+        gen_illegal_opcode(env, s, 3);

         break;

     }

@@ -1959,7 +1962,8 @@ static void disas_e5(DisasContext* s, uint64_t insn)

 }

 #endif

-static void disas_eb(DisasContext *s, int op, int r1, int r3, int b2, int d2)

+static void disas_eb(CPUS390XState *env, DisasContext *s, int op, int r1,

+                     int r3, int b2, int d2)

 {

     TCGv_i64 tmp, tmp2, tmp3, tmp4;

     TCGv_i32 tmp32_1, tmp32_2;

@@ -2102,7 +2106,7 @@ do_mh:

 #ifndef CONFIG_USER_ONLY

     case 0x2f: /* LCTLG     R1,R3,D2(B2)     [RSE] */

         /* Load Control */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         tmp = get_address(s, 0, b2, d2);

         tmp32_1 = tcg_const_i32(r1);

         tmp32_2 = tcg_const_i32(r3);

@@ -2114,7 +2118,7 @@ do_mh:

         break;

     case 0x25: /* STCTG     R1,R3,D2(B2)     [RSE] */

         /* Store Control */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         tmp = get_address(s, 0, b2, d2);

         tmp32_1 = tcg_const_i32(r1);

         tmp32_2 = tcg_const_i32(r3);

@@ -2191,13 +2195,13 @@ do_mh:

         break;

     default:

         LOG_DISAS("illegal eb operation 0x%x\n", op);

-        gen_illegal_opcode(s, ilc);

+        gen_illegal_opcode(env, s, ilc);

         break;

     }

 }

-static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,

-                     int r1b)

+static void disas_ed(CPUS390XState *env, DisasContext *s, int op, int r1,

+                     int x2, int b2, int d2, int r1b)

 {

     TCGv_i32 tmp_r1, tmp32;

     TCGv_i64 addr, tmp;

@@ -2311,14 +2315,15 @@ static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,

         break;

     default:

         LOG_DISAS("illegal ed operation 0x%x\n", op);

-        gen_illegal_opcode(s, 3);

+        gen_illegal_opcode(env, s, 3);

         return;

     }

     tcg_temp_free_i32(tmp_r1);

     tcg_temp_free_i64(addr);

 }

-static void disas_a5(DisasContext *s, int op, int r1, int i2)

+static void disas_a5(CPUS390XState *env, DisasContext *s, int op, int r1,

+                     int i2)

 {

     TCGv_i64 tmp, tmp2;

     TCGv_i32 tmp32;

@@ -2467,12 +2472,13 @@ static void disas_a5(DisasContext *s, int op, int r1, int i2)

         break;

     default:

         LOG_DISAS("illegal a5 operation 0x%x\n", op);

-        gen_illegal_opcode(s, 2);

+        gen_illegal_opcode(env, s, 2);

         return;

     }

 }

-static void disas_a7(DisasContext *s, int op, int r1, int i2)

+static void disas_a7(CPUS390XState *env, DisasContext *s, int op, int r1,

+                     int i2)

 {

     TCGv_i64 tmp, tmp2;

     TCGv_i32 tmp32_1, tmp32_2, tmp32_3;

@@ -2604,12 +2610,13 @@ static void disas_a7(DisasContext *s, int op, int r1, int i2)

         break;

     default:

         LOG_DISAS("illegal a7 operation 0x%x\n", op);

-        gen_illegal_opcode(s, 2);

+        gen_illegal_opcode(env, s, 2);

         return;

     }

 }

-static void disas_b2(DisasContext *s, int op, uint32_t insn)

+static void disas_b2(CPUS390XState *env, DisasContext *s, int op,

+                     uint32_t insn)

 {

     TCGv_i64 tmp, tmp2, tmp3;

     TCGv_i32 tmp32_1, tmp32_2, tmp32_3;

@@ -2708,7 +2715,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

 #ifndef CONFIG_USER_ONLY

     case 0x02: /* STIDP     D2(B2)     [S] */

         /* Store CPU ID */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         decode_rs(s, insn, &r1, &r3, &b2, &d2;;

         tmp = get_address(s, 0, b2, d2);

         potential_page_fault(s);

@@ -2717,7 +2724,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x04: /* SCK       D2(B2)     [S] */

         /* Set Clock */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         decode_rs(s, insn, &r1, &r3, &b2, &d2;;

         tmp = get_address(s, 0, b2, d2);

         potential_page_fault(s);

@@ -2736,7 +2743,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x06: /* SCKC     D2(B2)     [S] */

         /* Set Clock Comparator */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         decode_rs(s, insn, &r1, &r3, &b2, &d2;;

         tmp = get_address(s, 0, b2, d2);

         potential_page_fault(s);

@@ -2745,7 +2752,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x07: /* STCKC    D2(B2)     [S] */

         /* Store Clock Comparator */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         decode_rs(s, insn, &r1, &r3, &b2, &d2;;

         tmp = get_address(s, 0, b2, d2);

         potential_page_fault(s);

@@ -2754,7 +2761,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x08: /* SPT      D2(B2)     [S] */

         /* Set CPU Timer */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         decode_rs(s, insn, &r1, &r3, &b2, &d2;;

         tmp = get_address(s, 0, b2, d2);

         potential_page_fault(s);

@@ -2763,7 +2770,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x09: /* STPT     D2(B2)     [S] */

         /* Store CPU Timer */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         decode_rs(s, insn, &r1, &r3, &b2, &d2;;

         tmp = get_address(s, 0, b2, d2);

         potential_page_fault(s);

@@ -2772,7 +2779,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x0a: /* SPKA     D2(B2)     [S] */

         /* Set PSW Key from Address */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         decode_rs(s, insn, &r1, &r3, &b2, &d2;;

         tmp = get_address(s, 0, b2, d2);

         tmp2 = tcg_temp_new_i64();

@@ -2784,12 +2791,12 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x0d: /* PTLB                [S] */

         /* Purge TLB */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         gen_helper_ptlb(cpu_env);

         break;

     case 0x10: /* SPX      D2(B2)     [S] */

         /* Set Prefix Register */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         decode_rs(s, insn, &r1, &r3, &b2, &d2;;

         tmp = get_address(s, 0, b2, d2);

         potential_page_fault(s);

@@ -2798,7 +2805,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x11: /* STPX     D2(B2)     [S] */

         /* Store Prefix */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         decode_rs(s, insn, &r1, &r3, &b2, &d2;;

         tmp = get_address(s, 0, b2, d2);

         tmp2 = tcg_temp_new_i64();

@@ -2809,7 +2816,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x12: /* STAP     D2(B2)     [S] */

         /* Store CPU Address */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         decode_rs(s, insn, &r1, &r3, &b2, &d2;;

         tmp = get_address(s, 0, b2, d2);

         tmp2 = tcg_temp_new_i64();

@@ -2823,7 +2830,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x21: /* IPTE     R1,R2      [RRE] */

         /* Invalidate PTE */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         r1 = (insn >> 4) & 0xf;

         r2 = insn & 0xf;

         tmp = load_reg(r1);

@@ -2834,7 +2841,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x29: /* ISKE     R1,R2      [RRE] */

         /* Insert Storage Key Extended */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         r1 = (insn >> 4) & 0xf;

         r2 = insn & 0xf;

         tmp = load_reg(r2);

@@ -2846,7 +2853,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x2a: /* RRBE     R1,R2      [RRE] */

         /* Set Storage Key Extended */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         r1 = (insn >> 4) & 0xf;

         r2 = insn & 0xf;

         tmp32_1 = load_reg32(r1);

@@ -2858,7 +2865,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x2b: /* SSKE     R1,R2      [RRE] */

         /* Set Storage Key Extended */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         r1 = (insn >> 4) & 0xf;

         r2 = insn & 0xf;

         tmp32_1 = load_reg32(r1);

@@ -2869,12 +2876,12 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x34: /* STCH ? */

         /* Store Subchannel */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         gen_op_movi_cc(s, 3);

         break;

     case 0x46: /* STURA    R1,R2      [RRE] */

         /* Store Using Real Address */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         r1 = (insn >> 4) & 0xf;

         r2 = insn & 0xf;

         tmp32_1 = load_reg32(r1);

@@ -2886,7 +2893,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x50: /* CSP      R1,R2      [RRE] */

         /* Compare And Swap And Purge */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         r1 = (insn >> 4) & 0xf;

         r2 = insn & 0xf;

         tmp32_1 = tcg_const_i32(r1);

@@ -2898,7 +2905,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x5f: /* CHSC ? */

         /* Channel Subsystem Call */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         gen_op_movi_cc(s, 3);

         break;

     case 0x78: /* STCKE    D2(B2)     [S] */

@@ -2912,7 +2919,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x79: /* SACF    D2(B2)     [S] */

         /* Store Clock Extended */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         decode_rs(s, insn, &r1, &r3, &b2, &d2;;

         tmp = get_address(s, 0, b2, d2);

         potential_page_fault(s);

@@ -2924,7 +2931,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         s->is_jmp = DISAS_EXCP;

         break;

     case 0x7d: /* STSI     D2,(B2)     [S] */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         decode_rs(s, insn, &r1, &r3, &b2, &d2;;

         tmp = get_address(s, 0, b2, d2);

         tmp32_1 = load_reg32(0);

@@ -2950,7 +2957,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0xb1: /* STFL     D2(B2)     [S] */

         /* Store Facility List (CPU features) at 200 */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         tmp2 = tcg_const_i64(0xc0000000);

         tmp = tcg_const_i64(200);

         tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));

@@ -2959,7 +2966,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0xb2: /* LPSWE    D2(B2)     [S] */

         /* Load PSW Extended */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         decode_rs(s, insn, &r1, &r3, &b2, &d2;;

         tmp = get_address(s, 0, b2, d2);

         tmp2 = tcg_temp_new_i64();

@@ -2976,7 +2983,7 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

         break;

     case 0x20: /* SERVC     R1,R2     [RRE] */

         /* SCLP Service call (PV hypercall) */

-        check_privileged(s, ilc);

+        check_privileged(env, s, ilc);

         potential_page_fault(s);

         tmp32_1 = load_reg32(r2);

         tmp = load_reg(r1);

@@ -2988,12 +2995,13 @@ static void disas_b2(DisasContext *s, int op, uint32_t insn)

 #endif

     default:

         LOG_DISAS("illegal b2 operation 0x%x\n", op);

-        gen_illegal_opcode(s, ilc);

+        gen_illegal_opcode(env, s, ilc);

         break;

     }

 }

-static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)

+static void disas_b3(CPUS390XState *env, DisasContext *s, int op, int m3,

+                     int r1, int r2)

 {

     TCGv_i64 tmp;

     TCGv_i32 tmp32_1, tmp32_2, tmp32_3;

@@ -3263,7 +3271,7 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)

         break;

     default:

         LOG_DISAS("illegal b3 operation 0x%x\n", op);

-        gen_illegal_opcode(s, 2);

+        gen_illegal_opcode(env, s, 2);

         break;

     }

@@ -3271,7 +3279,8 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)

 #undef FP_HELPER

 }

-static void disas_b9(DisasContext *s, int op, int r1, int r2)

+static void disas_b9(CPUS390XState *env, DisasContext *s, int op, int r1,

+                     int r2)

 {

     TCGv_i64 tmp, tmp2, tmp3;

     TCGv_i32 tmp32_1, tmp32_2, tmp32_3;

@@ -3654,12 +3663,12 @@ static void disas_b9(DisasContext *s, int op, int r1, int r2)

         break;

     default:

         LOG_DISAS("illegal b9 operation 0x%x\n", op);

-        gen_illegal_opcode(s, 2);

+        gen_illegal_opcode(env, s, 2);

         break;

     }

 }

-static void disas_c0(DisasContext *s, int op, int r1, int i2)

+static void disas_c0(CPUS390XState *env, DisasContext *s, int op, int r1, int i2)

 {

     TCGv_i64 tmp;

     TCGv_i32 tmp32_1, tmp32_2;

@@ -3755,12 +3764,13 @@ static void disas_c0(DisasContext *s, int op, int r1, int i2)

         break;

     default:

         LOG_DISAS("illegal c0 operation 0x%x\n", op);

-        gen_illegal_opcode(s, 3);

+        gen_illegal_opcode(env, s, 3);

         break;

     }

 }

-static void disas_c2(DisasContext *s, int op, int r1, int i2)

+static void disas_c2(CPUS390XState *env, DisasContext *s, int op, int r1,

+                     int i2)

 {

     TCGv_i64 tmp, tmp2, tmp3;

     TCGv_i32 tmp32_1, tmp32_2, tmp32_3;

@@ -3832,7 +3842,7 @@ static void disas_c2(DisasContext *s, int op, int r1, int i2)

         break;

     default:

         LOG_DISAS("illegal c2 operation 0x%x\n", op);

-        gen_illegal_opcode(s, 3);

+        gen_illegal_opcode(env, s, 3);

         break;

     }

 }

@@ -3854,7 +3864,7 @@ static void gen_and_or_xor_i32(int opc, TCGv_i32 tmp, TCGv_i32 tmp2)

     }

 }

-static void disas_s390_insn(DisasContext *s)

+static void disas_s390_insn(CPUS390XState *env, DisasContext *s)

 {

     TCGv_i64 tmp, tmp2, tmp3, tmp4;

     TCGv_i32 tmp32_1, tmp32_2, tmp32_3, tmp32_4;

@@ -3865,7 +3875,7 @@ static void disas_s390_insn(DisasContext *s)

     int ilc;

     int l1;

-    opc = cpu_ldub_code(cpu_single_env, s->pc);

+    opc = cpu_ldub_code(env, s->pc);

     LOG_DISAS("opc 0x%x\n", opc);

     ilc = get_ilc(opc);

@@ -3873,12 +3883,12 @@ static void disas_s390_insn(DisasContext *s)

     switch (opc) {

 #ifndef CONFIG_USER_ONLY

     case 0x01: /* SAM */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         /* set addressing mode, but we only do 64bit anyways */

         break;

 #endif

     case 0x6: /* BCTR     R1,R2     [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp32_1 = load_reg32(r1);

         tcg_gen_subi_i32(tmp32_1, tmp32_1, 1);

@@ -3904,7 +3914,7 @@ static void disas_s390_insn(DisasContext *s)

         }

         break;

     case 0x7: /* BCR    M1,R2     [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         if (r2) {

             tmp = load_reg(r2);

@@ -3916,7 +3926,7 @@ static void disas_s390_insn(DisasContext *s)

         }

         break;

     case 0xa: /* SVC    I         [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         debug_insn(insn);

         i = insn & 0xff;

         update_psw_addr(s);

@@ -3933,7 +3943,7 @@ static void disas_s390_insn(DisasContext *s)

         tcg_temp_free_i32(tmp32_3);

         break;

     case 0xd: /* BASR   R1,R2     [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp = tcg_const_i64(pc_to_link_info(s, s->pc + 2));

         store_reg(r1, tmp);

@@ -3946,7 +3956,7 @@ static void disas_s390_insn(DisasContext *s)

         tcg_temp_free_i64(tmp);

         break;

     case 0xe: /* MVCL   R1,R2     [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp32_1 = tcg_const_i32(r1);

         tmp32_2 = tcg_const_i32(r2);

@@ -3957,7 +3967,7 @@ static void disas_s390_insn(DisasContext *s)

         tcg_temp_free_i32(tmp32_2);

         break;

     case 0x10: /* LPR    R1,R2     [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp32_1 = load_reg32(r2);

         set_cc_abs32(s, tmp32_1);

@@ -3966,7 +3976,7 @@ static void disas_s390_insn(DisasContext *s)

         tcg_temp_free_i32(tmp32_1);

         break;

     case 0x11: /* LNR    R1,R2     [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp32_1 = load_reg32(r2);

         set_cc_nabs32(s, tmp32_1);

@@ -3975,7 +3985,7 @@ static void disas_s390_insn(DisasContext *s)

         tcg_temp_free_i32(tmp32_1);

         break;

     case 0x12: /* LTR    R1,R2     [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp32_1 = load_reg32(r2);

         if (r1 != r2) {

@@ -3985,7 +3995,7 @@ static void disas_s390_insn(DisasContext *s)

         tcg_temp_free_i32(tmp32_1);

         break;

     case 0x13: /* LCR    R1,R2     [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp32_1 = load_reg32(r2);

         tcg_gen_neg_i32(tmp32_1, tmp32_1);

@@ -3996,7 +4006,7 @@ static void disas_s390_insn(DisasContext *s)

     case 0x14: /* NR     R1,R2     [RR] */

     case 0x16: /* OR     R1,R2     [RR] */

     case 0x17: /* XR     R1,R2     [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp32_2 = load_reg32(r2);

         tmp32_1 = load_reg32(r1);

@@ -4007,7 +4017,7 @@ static void disas_s390_insn(DisasContext *s)

         tcg_temp_free_i32(tmp32_2);

         break;

     case 0x18: /* LR     R1,R2     [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp32_1 = load_reg32(r2);

         store_reg32(r1, tmp32_1);

@@ -4015,7 +4025,7 @@ static void disas_s390_insn(DisasContext *s)

         break;

     case 0x15: /* CLR    R1,R2     [RR] */

     case 0x19: /* CR     R1,R2     [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp32_1 = load_reg32(r1);

         tmp32_2 = load_reg32(r2);

@@ -4029,7 +4039,7 @@ static void disas_s390_insn(DisasContext *s)

         break;

     case 0x1a: /* AR     R1,R2     [RR] */

     case 0x1e: /* ALR    R1,R2     [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp32_1 = load_reg32(r1);

         tmp32_2 = load_reg32(r2);

@@ -4047,7 +4057,7 @@ static void disas_s390_insn(DisasContext *s)

         break;

     case 0x1b: /* SR     R1,R2     [RR] */

     case 0x1f: /* SLR    R1,R2     [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp32_1 = load_reg32(r1);

         tmp32_2 = load_reg32(r2);

@@ -4065,7 +4075,7 @@ static void disas_s390_insn(DisasContext *s)

         break;

     case 0x1c: /* MR     R1,R2     [RR] */

         /* reg(r1, r1+1) = reg(r1+1) * reg(r2) */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp2 = load_reg(r2);

         tmp3 = load_reg((r1 + 1) & 15);

@@ -4079,7 +4089,7 @@ static void disas_s390_insn(DisasContext *s)

         tcg_temp_free_i64(tmp3);

         break;

     case 0x1d: /* DR     R1,R2               [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp32_1 = load_reg32(r1);

         tmp32_2 = load_reg32(r1 + 1);

@@ -4114,21 +4124,21 @@ static void disas_s390_insn(DisasContext *s)

         tcg_temp_free_i64(tmp3);

         break;

     case 0x28: /* LDR    R1,R2               [RR] */

-        insn = ld_code2(s->pc);

+        insn = ld_code2(env, s->pc);

         decode_rr(s, insn, &r1, &r2;;

         tmp = load_freg(r2);

         store_freg(r1, tmp);

         tcg_temp_free_i64(tmp);

         break;

     case 0x38: /* LER    R1,R2               [RR] */

-        insn = ld_code2(s->pc);