peterdelevoryas / rpms / qemu

Forked from rpms/qemu 2 years ago
Clone

Blame 0016-target-ppc-gdbstub-fix-altivec-registers-for-little-.patch

7d975d
From: Greg Kurz <gkurz@linux.vnet.ibm.com>
7d975d
Date: Fri, 15 Jan 2016 16:00:38 +0100
7d975d
Subject: [PATCH] target-ppc: gdbstub: fix altivec registers for little-endian
7d975d
 guests
7d975d
7d975d
Altivec registers are 128-bit wide. They are stored in memory as two
7d975d
64-bit values that must be byteswapped when the guest is little-endian.
7d975d
Let's reuse the ppc_maybe_bswap_register() helper for this.
7d975d
7d975d
We also need to fix the ordering of the 64-bit elements according to
7d975d
the target endianness, for both system and user mode.
7d975d
7d975d
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
7d975d
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
7d975d
(cherry picked from commit ea499e71506c91aa259a7fdccf1d6b2022f5b530)
7d975d
---
7d975d
 target-ppc/translate_init.c | 12 ++++++++++--
7d975d
 1 file changed, 10 insertions(+), 2 deletions(-)
7d975d
7d975d
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
7d975d
index 18e9e56..80d53e4 100644
7d975d
--- a/target-ppc/translate_init.c
7d975d
+++ b/target-ppc/translate_init.c
7d975d
@@ -8754,9 +8754,9 @@ static void dump_ppc_insns (CPUPPCState *env)
7d975d
 static bool avr_need_swap(CPUPPCState *env)
7d975d
 {
7d975d
 #ifdef HOST_WORDS_BIGENDIAN
7d975d
-    return false;
7d975d
+    return msr_le;
7d975d
 #else
7d975d
-    return true;
7d975d
+    return !msr_le;
7d975d
 #endif
7d975d
 }
7d975d
 
7d975d
@@ -8800,14 +8800,18 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7d975d
             stq_p(mem_buf, env->avr[n].u64[1]);
7d975d
             stq_p(mem_buf+8, env->avr[n].u64[0]);
7d975d
         }
7d975d
+        ppc_maybe_bswap_register(env, mem_buf, 8);
7d975d
+        ppc_maybe_bswap_register(env, mem_buf + 8, 8);
7d975d
         return 16;
7d975d
     }
7d975d
     if (n == 32) {
7d975d
         stl_p(mem_buf, env->vscr);
7d975d
+        ppc_maybe_bswap_register(env, mem_buf, 4);
7d975d
         return 4;
7d975d
     }
7d975d
     if (n == 33) {
7d975d
         stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
7d975d
+        ppc_maybe_bswap_register(env, mem_buf, 4);
7d975d
         return 4;
7d975d
     }
7d975d
     return 0;
7d975d
@@ -8816,6 +8820,8 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7d975d
 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7d975d
 {
7d975d
     if (n < 32) {
7d975d
+        ppc_maybe_bswap_register(env, mem_buf, 8);
7d975d
+        ppc_maybe_bswap_register(env, mem_buf + 8, 8);
7d975d
         if (!avr_need_swap(env)) {
7d975d
             env->avr[n].u64[0] = ldq_p(mem_buf);
7d975d
             env->avr[n].u64[1] = ldq_p(mem_buf+8);
7d975d
@@ -8826,10 +8832,12 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7d975d
         return 16;
7d975d
     }
7d975d
     if (n == 32) {
7d975d
+        ppc_maybe_bswap_register(env, mem_buf, 4);
7d975d
         env->vscr = ldl_p(mem_buf);
7d975d
         return 4;
7d975d
     }
7d975d
     if (n == 33) {
7d975d
+        ppc_maybe_bswap_register(env, mem_buf, 4);
7d975d
         env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
7d975d
         return 4;
7d975d
     }