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From bb8136df698bd565ee4f6c18d26c50dee320bfe4 Mon Sep 17 00:00:00 2001
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From: Pan Nengyuan <pannengyuan@huawei.com>
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Date: Tue, 10 Dec 2019 15:14:37 +0800
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Subject: [PATCH 1/5] riscv/sifive_u: fix a memory leak in soc_realize()
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Fix a minor memory leak in riscv_sifive_u_soc_realize()
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Reported-by: Euler Robot <euler.robot@huawei.com>
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Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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---
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hw/riscv/sifive_u.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
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index 0140e95732..0e12b3ccef 100644
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--- a/hw/riscv/sifive_u.c
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+++ b/hw/riscv/sifive_u.c
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@@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
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SIFIVE_U_PLIC_CONTEXT_BASE,
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SIFIVE_U_PLIC_CONTEXT_STRIDE,
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memmap[SIFIVE_U_PLIC].size);
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+ g_free(plic_hart_config);
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sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
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serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
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sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
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--
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2.24.1
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