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		00db10	`commit a88dadbed5d7589ac7880efe62ea511844107795`
		00db10	`Author: Wilco <wdijkstr@arm.com>`
		00db10	`Date: Mon Jun 2 12:44:21 2014 +0100`
		00db10
		00db10	`[AArch64] Remove ISB after FPCR write.`
		00db10
		00db10	`diff --git a/ports/sysdeps/aarch64/fpu/fpu_control.h b/ports/sysdeps/aarch64/fpu/fpu_control.h`
		00db10	`index 6a265e8..d5a890d 100644`
		00db10	`--- a/ports/sysdeps/aarch64/fpu/fpu_control.h`
		00db10	`+++ b/ports/sysdeps/aarch64/fpu/fpu_control.h`
		00db10	`@@ -24,11 +24,8 @@`
		00db10	`#define _FPU_GETCW(fpcr) \`
		00db10	`__asm__ __volatile__ ("mrs %0, fpcr" : "=r" (fpcr))`
		00db10
		00db10	`-#define _FPU_SETCW(fpcr) \`
		00db10	`- { \`
		00db10	`- __asm__ __volatile__ ("msr fpcr, %0" : : "r" (fpcr)); \`
		00db10	`- __asm__ __volatile__ ("isb"); \`
		00db10	`- }`
		00db10	`+#define _FPU_SETCW(fpcr) \`
		00db10	`+ __asm__ __volatile__ ("msr fpcr, %0" : : "r" (fpcr))`
		00db10
		00db10	`#define _FPU_GETFPSR(fpsr) \`
		00db10	`__asm__ __volatile__ ("mrs %0, fpsr" : "=r" (fpsr))`