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commit aecf33aa70331670c06db6b652712b476e24051c
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Author: Muralidhara M K <muralimk@amd.com>
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Date: Mon Jul 12 05:40:46 2021 -0500
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rasdaemon: Enumerate memory on noncpu nodes
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On newer heterogeneous systems from AMD with GPU nodes (with HBM2 memory
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banks) connected via xGMI links to the CPUs.
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The node id information is available in the InstanceHI[47:44] of
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the IPID register.
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The UMC Phys on Aldeberan nodes are enumerated as csrow
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The UMC channels connected to HBMs are enumerated as ranks.
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Signed-off-by: Muralidhara M K <muralimk@amd.com>
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Signed-off-by: Naveen Krishna Chatradhi <nchatrad@amd.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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diff --git a/mce-amd-smca.c b/mce-amd-smca.c
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index 3c346f4..f3379fc 100644
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--- a/mce-amd-smca.c
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+++ b/mce-amd-smca.c
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@@ -78,6 +78,12 @@ enum smca_bank_types {
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/* Maximum number of MCA banks per CPU. */
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#define MAX_NR_BANKS 64
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+/*
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+ * On Newer heterogeneous systems from AMD with CPU and GPU nodes connected
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+ * via xGMI links, the NON CPU Nodes are enumerated from index 8
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+ */
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+#define NONCPU_NODE_INDEX 8
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+
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/* SMCA Extended error strings */
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/* Load Store */
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static const char * const smca_ls_mce_desc[] = {
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@@ -531,6 +537,26 @@ static int find_umc_channel(struct mce_event *e)
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{
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return EXTRACT(e->ipid, 0, 31) >> 20;
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}
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+
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+/*
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+ * The HBM memory managed by the UMCCH of the noncpu node
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+ * can be calculated based on the [15:12]bits of IPID
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+ */
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+static int find_hbm_channel(struct mce_event *e)
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+{
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+ int umc, tmp;
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+
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+ umc = EXTRACT(e->ipid, 0, 31) >> 20;
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+
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+ /*
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+ * The HBM channel managed by the UMC of the noncpu node
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+ * can be calculated based on the [15:12]bits of IPID as follows
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+ */
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+ tmp = ((e->ipid >> 12) & 0xf);
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+
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+ return (umc % 2) ? tmp + 4 : tmp;
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+}
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+
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/* Decode extended errors according to Scalable MCA specification */
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static void decode_smca_error(struct mce_event *e)
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{
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@@ -539,6 +565,7 @@ static void decode_smca_error(struct mce_event *e)
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unsigned short xec = (e->status >> 16) & 0x3f;
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const struct smca_hwid *s_hwid;
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uint32_t mcatype_hwid = EXTRACT(e->ipid, 32, 63);
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+ uint8_t mcatype_instancehi = EXTRACT(e->ipid, 44, 47);
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unsigned int csrow = -1, channel = -1;
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unsigned int i;
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@@ -548,14 +575,16 @@ static void decode_smca_error(struct mce_event *e)
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bank_type = s_hwid->bank_type;
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break;
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}
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+ if (mcatype_instancehi >= NONCPU_NODE_INDEX)
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+ bank_type = SMCA_UMC_V2;
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}
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- if (i >= ARRAY_SIZE(smca_hwid_mcatypes)) {
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+ if (i >= MAX_NR_BANKS) {
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strcpy(e->mcastatus_msg, "Couldn't find bank type with IPID");
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return;
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}
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- if (bank_type >= N_SMCA_BANK_TYPES) {
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+ if (bank_type >= MAX_NR_BANKS) {
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strcpy(e->mcastatus_msg, "Don't know how to decode this bank");
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return;
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}
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@@ -580,6 +609,16 @@ static void decode_smca_error(struct mce_event *e)
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mce_snprintf(e->mc_location, "memory_channel=%d,csrow=%d",
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channel, csrow);
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}
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+
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+ if (bank_type == SMCA_UMC_V2 && xec == 0) {
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+ /* The UMCPHY is reported as csrow in case of noncpu nodes */
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+ csrow = find_umc_channel(e) / 2;
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+ /* UMCCH is managing the HBM memory */
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+ channel = find_hbm_channel(e);
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+ mce_snprintf(e->mc_location, "memory_channel=%d,csrow=%d",
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+ channel, csrow);
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+ }
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+
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}
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int parse_amd_smca_event(struct ras_events *ras, struct mce_event *e)
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