ignatenkobrain / rpms / kernel

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From 371f6ca7f5cbad70f6e5fafc12d5448d7b6f0750 Mon Sep 17 00:00:00 2001
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From: Arthur Kiyanovski <akiyano@amazon.com>
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Date: Thu, 11 Oct 2018 11:26:16 +0300
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Subject: [PATCH 02/16] net: ena: minor performance improvement
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Reduce fastpath overhead by making ena_com_tx_comp_req_id_get() inline.
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Also move it to ena_eth_com.h file with its dependency function
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ena_com_cq_inc_head().
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Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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 drivers/net/ethernet/amazon/ena/ena_eth_com.c | 43 -----------------
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 drivers/net/ethernet/amazon/ena/ena_eth_com.h | 46 ++++++++++++++++++-
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 2 files changed, 44 insertions(+), 45 deletions(-)
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diff --git a/drivers/net/ethernet/amazon/ena/ena_eth_com.c b/drivers/net/ethernet/amazon/ena/ena_eth_com.c
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index 2b3ff0c20155..9c0511e9f9a2 100644
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--- a/drivers/net/ethernet/amazon/ena/ena_eth_com.c
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+++ b/drivers/net/ethernet/amazon/ena/ena_eth_com.c
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@@ -59,15 +59,6 @@ static inline struct ena_eth_io_rx_cdesc_base *ena_com_get_next_rx_cdesc(
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 	return cdesc;
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 }
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-static inline void ena_com_cq_inc_head(struct ena_com_io_cq *io_cq)
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-{
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-	io_cq->head++;
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-
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-	/* Switch phase bit in case of wrap around */
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-	if (unlikely((io_cq->head & (io_cq->q_depth - 1)) == 0))
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-		io_cq->phase ^= 1;
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-}
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-
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 static inline void *get_sq_desc(struct ena_com_io_sq *io_sq)
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 {
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 	u16 tail_masked;
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@@ -477,40 +468,6 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
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 	return 0;
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 }
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-int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id)
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-{
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-	u8 expected_phase, cdesc_phase;
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-	struct ena_eth_io_tx_cdesc *cdesc;
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-	u16 masked_head;
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-
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-	masked_head = io_cq->head & (io_cq->q_depth - 1);
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-	expected_phase = io_cq->phase;
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-
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-	cdesc = (struct ena_eth_io_tx_cdesc *)
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-		((uintptr_t)io_cq->cdesc_addr.virt_addr +
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-		(masked_head * io_cq->cdesc_entry_size_in_bytes));
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-
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-	/* When the current completion descriptor phase isn't the same as the
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-	 * expected, it mean that the device still didn't update
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-	 * this completion.
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-	 */
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-	cdesc_phase = READ_ONCE(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
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-	if (cdesc_phase != expected_phase)
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-		return -EAGAIN;
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-
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-	dma_rmb();
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-	if (unlikely(cdesc->req_id >= io_cq->q_depth)) {
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-		pr_err("Invalid req id %d\n", cdesc->req_id);
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-		return -EINVAL;
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-	}
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-
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-	ena_com_cq_inc_head(io_cq);
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-
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-	*req_id = READ_ONCE(cdesc->req_id);
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-
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-	return 0;
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-}
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-
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 bool ena_com_cq_empty(struct ena_com_io_cq *io_cq)
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 {
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 	struct ena_eth_io_rx_cdesc_base *cdesc;
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diff --git a/drivers/net/ethernet/amazon/ena/ena_eth_com.h b/drivers/net/ethernet/amazon/ena/ena_eth_com.h
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index 2f7657227cfe..4930324e9d8d 100644
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--- a/drivers/net/ethernet/amazon/ena/ena_eth_com.h
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+++ b/drivers/net/ethernet/amazon/ena/ena_eth_com.h
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@@ -86,8 +86,6 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
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 			       struct ena_com_buf *ena_buf,
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 			       u16 req_id);
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-int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id);
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-
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 bool ena_com_cq_empty(struct ena_com_io_cq *io_cq);
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 static inline void ena_com_unmask_intr(struct ena_com_io_cq *io_cq,
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@@ -159,4 +157,48 @@ static inline void ena_com_comp_ack(struct ena_com_io_sq *io_sq, u16 elem)
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 	io_sq->next_to_comp += elem;
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 }
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+static inline void ena_com_cq_inc_head(struct ena_com_io_cq *io_cq)
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+{
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+	io_cq->head++;
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+
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+	/* Switch phase bit in case of wrap around */
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+	if (unlikely((io_cq->head & (io_cq->q_depth - 1)) == 0))
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+		io_cq->phase ^= 1;
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+}
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+
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+static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq,
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+					     u16 *req_id)
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+{
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+	u8 expected_phase, cdesc_phase;
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+	struct ena_eth_io_tx_cdesc *cdesc;
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+	u16 masked_head;
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+
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+	masked_head = io_cq->head & (io_cq->q_depth - 1);
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+	expected_phase = io_cq->phase;
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+
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+	cdesc = (struct ena_eth_io_tx_cdesc *)
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+		((uintptr_t)io_cq->cdesc_addr.virt_addr +
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+		(masked_head * io_cq->cdesc_entry_size_in_bytes));
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+
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+	/* When the current completion descriptor phase isn't the same as the
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+	 * expected, it mean that the device still didn't update
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+	 * this completion.
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+	 */
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+	cdesc_phase = READ_ONCE(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
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+	if (cdesc_phase != expected_phase)
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+		return -EAGAIN;
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+
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+	dma_rmb();
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+
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+	*req_id = READ_ONCE(cdesc->req_id);
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+	if (unlikely(*req_id >= io_cq->q_depth)) {
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+		pr_err("Invalid req id %d\n", cdesc->req_id);
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+		return -EINVAL;
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+	}
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+
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+	ena_com_cq_inc_head(io_cq);
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+
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+	return 0;
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+}
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+
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 #endif /* ENA_ETH_COM_H_ */
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-- 
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2.19.1
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From df44a6755f48dfc5c94d878e80807931460c3846 Mon Sep 17 00:00:00 2001
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From: Arthur Kiyanovski <akiyano@amazon.com>
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Date: Thu, 11 Oct 2018 11:26:17 +0300
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Subject: [PATCH 03/16] net: ena: complete host info to match latest ENA spec
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Add new fields and definitions to host info and fill them
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according to the latest ENA spec version.
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Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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 .../net/ethernet/amazon/ena/ena_admin_defs.h  | 31 ++++++++++++++++++-
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 drivers/net/ethernet/amazon/ena/ena_com.c     | 12 +++----
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 .../net/ethernet/amazon/ena/ena_common_defs.h |  4 +--
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 drivers/net/ethernet/amazon/ena/ena_netdev.c  | 10 ++++--
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 4 files changed, 43 insertions(+), 14 deletions(-)
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diff --git a/drivers/net/ethernet/amazon/ena/ena_admin_defs.h b/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
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index 4532e574ebcd..d735164efea3 100644
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--- a/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
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+++ b/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
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@@ -63,6 +63,8 @@ enum ena_admin_aq_completion_status {
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 	ENA_ADMIN_ILLEGAL_PARAMETER		= 5,
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 	ENA_ADMIN_UNKNOWN_ERROR			= 6,
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+
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+	ENA_ADMIN_RESOURCE_BUSY                 = 7,
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 };
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 enum ena_admin_aq_feature_id {
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@@ -702,6 +704,10 @@ enum ena_admin_os_type {
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 	ENA_ADMIN_OS_FREEBSD	= 4,
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 	ENA_ADMIN_OS_IPXE	= 5,
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+
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+	ENA_ADMIN_OS_ESXI       = 6,
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+
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+	ENA_ADMIN_OS_GROUPS_NUM = 6,
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 };
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 struct ena_admin_host_info {
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@@ -723,11 +729,27 @@ struct ena_admin_host_info {
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 	/* 7:0 : major
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 	 * 15:8 : minor
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 	 * 23:16 : sub_minor
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+	 * 31:24 : module_type
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 	 */
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 	u32 driver_version;
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 	/* features bitmap */
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-	u32 supported_network_features[4];
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+	u32 supported_network_features[2];
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+
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+	/* ENA spec version of driver */
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+	u16 ena_spec_version;
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+
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+	/* ENA device's Bus, Device and Function
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+	 * 2:0 : function
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+	 * 7:3 : device
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+	 * 15:8 : bus
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+	 */
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+	u16 bdf;
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+
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+	/* Number of CPUs */
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+	u16 num_cpus;
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+
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+	u16 reserved;
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 };
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 struct ena_admin_rss_ind_table_entry {
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@@ -1008,6 +1030,13 @@ struct ena_admin_ena_mmio_req_read_less_resp {
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 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
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 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
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 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
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+#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
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+#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
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+#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
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+#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
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+#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
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+#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
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+#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
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 /* aenq_common_desc */
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 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
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diff --git a/drivers/net/ethernet/amazon/ena/ena_com.c b/drivers/net/ethernet/amazon/ena/ena_com.c
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index 7635c38e77dd..b6e6a4721931 100644
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--- a/drivers/net/ethernet/amazon/ena/ena_com.c
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+++ b/drivers/net/ethernet/amazon/ena/ena_com.c
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@@ -41,9 +41,6 @@
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 #define ENA_ASYNC_QUEUE_DEPTH 16
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 #define ENA_ADMIN_QUEUE_DEPTH 32
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-#define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \
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-		ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \
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-		| (ENA_COMMON_SPEC_VERSION_MINOR))
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 #define ENA_CTRL_MAJOR		0
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 #define ENA_CTRL_MINOR		0
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@@ -1400,11 +1397,6 @@ int ena_com_validate_version(struct ena_com_dev *ena_dev)
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 			ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
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 		ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
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-	if (ver < MIN_ENA_VER) {
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-		pr_err("ENA version is lower than the minimal version the driver supports\n");
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-		return -1;
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-	}
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-
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 	pr_info("ena controller version: %d.%d.%d implementation version %d\n",
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 		(ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >>
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 			ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
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@@ -2441,6 +2433,10 @@ int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
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 	if (unlikely(!host_attr->host_info))
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 		return -ENOMEM;
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+	host_attr->host_info->ena_spec_version =
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+		((ENA_COMMON_SPEC_VERSION_MAJOR << ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
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+		(ENA_COMMON_SPEC_VERSION_MINOR));
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+
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 	return 0;
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 }
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diff --git a/drivers/net/ethernet/amazon/ena/ena_common_defs.h b/drivers/net/ethernet/amazon/ena/ena_common_defs.h
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index bb8d73676eab..23beb7e7ed7b 100644
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--- a/drivers/net/ethernet/amazon/ena/ena_common_defs.h
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+++ b/drivers/net/ethernet/amazon/ena/ena_common_defs.h
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@@ -32,8 +32,8 @@
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 #ifndef _ENA_COMMON_H_
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 #define _ENA_COMMON_H_
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-#define ENA_COMMON_SPEC_VERSION_MAJOR	0 /*  */
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-#define ENA_COMMON_SPEC_VERSION_MINOR	10 /*  */
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+#define ENA_COMMON_SPEC_VERSION_MAJOR        2
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+#define ENA_COMMON_SPEC_VERSION_MINOR        0
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 /* ENA operates with 48-bit memory addresses. ena_mem_addr_t */
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 struct ena_common_mem_addr {
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diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
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index 69a49784b204..0c9c0d3ce856 100644
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--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
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+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
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@@ -2206,7 +2206,8 @@ static u16 ena_select_queue(struct net_device *dev, struct sk_buff *skb,
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 	return qid;
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 }
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-static void ena_config_host_info(struct ena_com_dev *ena_dev)
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+static void ena_config_host_info(struct ena_com_dev *ena_dev,
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+				 struct pci_dev *pdev)
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 {
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 	struct ena_admin_host_info *host_info;
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 	int rc;
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@@ -2220,6 +2221,7 @@ static void ena_config_host_info(struct ena_com_dev *ena_dev)
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 	host_info = ena_dev->host_attr.host_info;
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+	host_info->bdf = (pdev->bus->number << 8) | pdev->devfn;
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 	host_info->os_type = ENA_ADMIN_OS_LINUX;
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 	host_info->kernel_ver = LINUX_VERSION_CODE;
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 	strncpy(host_info->kernel_ver_str, utsname()->version,
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@@ -2230,7 +2232,9 @@ static void ena_config_host_info(struct ena_com_dev *ena_dev)
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 	host_info->driver_version =
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 		(DRV_MODULE_VER_MAJOR) |
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 		(DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
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-		(DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
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+		(DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) |
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+		("K"[0] << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT);
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+	host_info->num_cpus = num_online_cpus();
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 	rc = ena_com_set_host_attributes(ena_dev);
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 	if (rc) {
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@@ -2454,7 +2458,7 @@ static int ena_device_init(struct ena_com_dev *ena_dev, struct pci_dev *pdev,
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 	 */
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 	ena_com_set_admin_polling_mode(ena_dev, true);
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-	ena_config_host_info(ena_dev);
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+	ena_config_host_info(ena_dev, pdev);
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 	/* Get Device Attributes*/
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 	rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
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-- 
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2.19.1
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From 0a66e6d1fe86cb3d49fcd76057b4f7a50e0fe49a Mon Sep 17 00:00:00 2001
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From: Arthur Kiyanovski <akiyano@amazon.com>
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Date: Thu, 11 Oct 2018 11:26:18 +0300
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Subject: [PATCH 04/16] net: ena: introduce Low Latency Queues data structures
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 according to ENA spec
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Low Latency Queues(LLQ) allow usage of device's memory for descriptors
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and headers. Such queues decrease processing time since data is already
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located on the device when driver rings the doorbell.
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Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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 .../net/ethernet/amazon/ena/ena_admin_defs.h  | 90 ++++++++++++++++++-
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 drivers/net/ethernet/amazon/ena/ena_com.h     | 38 ++++++++
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 drivers/net/ethernet/amazon/ena/ena_netdev.c  |  6 +-
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 3 files changed, 128 insertions(+), 6 deletions(-)
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diff --git a/drivers/net/ethernet/amazon/ena/ena_admin_defs.h b/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
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index d735164efea3..b439ec1b3edb 100644
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--- a/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
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+++ b/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
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@@ -74,6 +74,8 @@ enum ena_admin_aq_feature_id {
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 	ENA_ADMIN_HW_HINTS			= 3,
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+	ENA_ADMIN_LLQ                           = 4,
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+
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 	ENA_ADMIN_RSS_HASH_FUNCTION		= 10,
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 	ENA_ADMIN_STATELESS_OFFLOAD_CONFIG	= 11,
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@@ -485,8 +487,85 @@ struct ena_admin_device_attr_feature_desc {
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 	u32 max_mtu;
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 };
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+enum ena_admin_llq_header_location {
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+	/* header is in descriptor list */
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+	ENA_ADMIN_INLINE_HEADER                     = 1,
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+	/* header in a separate ring, implies 16B descriptor list entry */
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+	ENA_ADMIN_HEADER_RING                       = 2,
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+};
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+
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+enum ena_admin_llq_ring_entry_size {
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+	ENA_ADMIN_LIST_ENTRY_SIZE_128B              = 1,
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+	ENA_ADMIN_LIST_ENTRY_SIZE_192B              = 2,
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+	ENA_ADMIN_LIST_ENTRY_SIZE_256B              = 4,
e336be
+};
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+
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+enum ena_admin_llq_num_descs_before_header {
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+	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0     = 0,
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+	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1     = 1,
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+	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2     = 2,
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+	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4     = 4,
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+	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8     = 8,
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+};
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+
e336be
+/* packet descriptor list entry always starts with one or more descriptors,
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+ * followed by a header. The rest of the descriptors are located in the
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+ * beginning of the subsequent entry. Stride refers to how the rest of the
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+ * descriptors are placed. This field is relevant only for inline header
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+ * mode
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+ */
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+enum ena_admin_llq_stride_ctrl {
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+	ENA_ADMIN_SINGLE_DESC_PER_ENTRY             = 1,
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+	ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY          = 2,
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+};
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+
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+struct ena_admin_feature_llq_desc {
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+	u32 max_llq_num;
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+
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+	u32 max_llq_depth;
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+
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+	/*  specify the header locations the device supports. bitfield of
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+	 *    enum ena_admin_llq_header_location.
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+	 */
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+	u16 header_location_ctrl_supported;
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+
e336be
+	/* the header location the driver selected to use. */
e336be
+	u16 header_location_ctrl_enabled;
e336be
+
e336be
+	/* if inline header is specified - this is the size of descriptor
e336be
+	 *    list entry. If header in a separate ring is specified - this is
e336be
+	 *    the size of header ring entry. bitfield of enum
e336be
+	 *    ena_admin_llq_ring_entry_size. specify the entry sizes the device
e336be
+	 *    supports
e336be
+	 */
e336be
+	u16 entry_size_ctrl_supported;
e336be
+
e336be
+	/* the entry size the driver selected to use. */
e336be
+	u16 entry_size_ctrl_enabled;
e336be
+
e336be
+	/* valid only if inline header is specified. First entry associated
e336be
+	 *    with the packet includes descriptors and header. Rest of the
e336be
+	 *    entries occupied by descriptors. This parameter defines the max
e336be
+	 *    number of descriptors precedding the header in the first entry.
e336be
+	 *    The field is bitfield of enum
e336be
+	 *    ena_admin_llq_num_descs_before_header and specify the values the
e336be
+	 *    device supports
e336be
+	 */
e336be
+	u16 desc_num_before_header_supported;
e336be
+
e336be
+	/* the desire field the driver selected to use */
e336be
+	u16 desc_num_before_header_enabled;
e336be
+
e336be
+	/* valid only if inline was chosen. bitfield of enum
e336be
+	 *    ena_admin_llq_stride_ctrl
e336be
+	 */
e336be
+	u16 descriptors_stride_ctrl_supported;
e336be
+
e336be
+	/* the stride control the driver selected to use */
e336be
+	u16 descriptors_stride_ctrl_enabled;
e336be
+};
e336be
+
e336be
 struct ena_admin_queue_feature_desc {
e336be
-	/* including LLQs */
e336be
 	u32 max_sq_num;
e336be
 
e336be
 	u32 max_sq_depth;
e336be
@@ -495,9 +574,9 @@ struct ena_admin_queue_feature_desc {
e336be
 
e336be
 	u32 max_cq_depth;
e336be
 
e336be
-	u32 max_llq_num;
e336be
+	u32 max_legacy_llq_num;
e336be
 
e336be
-	u32 max_llq_depth;
e336be
+	u32 max_legacy_llq_depth;
e336be
 
e336be
 	u32 max_header_size;
e336be
 
e336be
@@ -822,6 +901,8 @@ struct ena_admin_get_feat_resp {
e336be
 
e336be
 		struct ena_admin_device_attr_feature_desc dev_attr;
e336be
 
e336be
+		struct ena_admin_feature_llq_desc llq;
e336be
+
e336be
 		struct ena_admin_queue_feature_desc max_queue;
e336be
 
e336be
 		struct ena_admin_feature_aenq_desc aenq;
e336be
@@ -869,6 +950,9 @@ struct ena_admin_set_feat_cmd {
e336be
 
e336be
 		/* rss indirection table */
e336be
 		struct ena_admin_feature_rss_ind_table ind_table;
e336be
+
e336be
+		/* LLQ configuration */
e336be
+		struct ena_admin_feature_llq_desc llq;
e336be
 	} u;
e336be
 };
e336be
 
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_com.h b/drivers/net/ethernet/amazon/ena/ena_com.h
e336be
index 7b784f8a06a6..50e6c8f6f138 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_com.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_com.h
e336be
@@ -108,6 +108,14 @@ enum ena_intr_moder_level {
e336be
 	ENA_INTR_MAX_NUM_OF_LEVELS,
e336be
 };
e336be
 
e336be
+struct ena_llq_configurations {
e336be
+	enum ena_admin_llq_header_location llq_header_location;
e336be
+	enum ena_admin_llq_ring_entry_size llq_ring_entry_size;
e336be
+	enum ena_admin_llq_stride_ctrl  llq_stride_ctrl;
e336be
+	enum ena_admin_llq_num_descs_before_header llq_num_decs_before_header;
e336be
+	u16 llq_ring_entry_size_value;
e336be
+};
e336be
+
e336be
 struct ena_intr_moder_entry {
e336be
 	unsigned int intr_moder_interval;
e336be
 	unsigned int pkts_per_interval;
e336be
@@ -142,6 +150,15 @@ struct ena_com_tx_meta {
e336be
 	u16 l4_hdr_len; /* In words */
e336be
 };
e336be
 
e336be
+struct ena_com_llq_info {
e336be
+	u16 header_location_ctrl;
e336be
+	u16 desc_stride_ctrl;
e336be
+	u16 desc_list_entry_size_ctrl;
e336be
+	u16 desc_list_entry_size;
e336be
+	u16 descs_num_before_header;
e336be
+	u16 descs_per_entry;
e336be
+};
e336be
+
e336be
 struct ena_com_io_cq {
e336be
 	struct ena_com_io_desc_addr cdesc_addr;
e336be
 
e336be
@@ -179,6 +196,20 @@ struct ena_com_io_cq {
e336be
 
e336be
 } ____cacheline_aligned;
e336be
 
e336be
+struct ena_com_io_bounce_buffer_control {
e336be
+	u8 *base_buffer;
e336be
+	u16 next_to_use;
e336be
+	u16 buffer_size;
e336be
+	u16 buffers_num;  /* Must be a power of 2 */
e336be
+};
e336be
+
e336be
+/* This struct is to keep tracking the current location of the next llq entry */
e336be
+struct ena_com_llq_pkt_ctrl {
e336be
+	u8 *curr_bounce_buf;
e336be
+	u16 idx;
e336be
+	u16 descs_left_in_line;
e336be
+};
e336be
+
e336be
 struct ena_com_io_sq {
e336be
 	struct ena_com_io_desc_addr desc_addr;
e336be
 
e336be
@@ -190,6 +221,9 @@ struct ena_com_io_sq {
e336be
 
e336be
 	u32 msix_vector;
e336be
 	struct ena_com_tx_meta cached_tx_meta;
e336be
+	struct ena_com_llq_info llq_info;
e336be
+	struct ena_com_llq_pkt_ctrl llq_buf_ctrl;
e336be
+	struct ena_com_io_bounce_buffer_control bounce_buf_ctrl;
e336be
 
e336be
 	u16 q_depth;
e336be
 	u16 qid;
e336be
@@ -197,6 +231,7 @@ struct ena_com_io_sq {
e336be
 	u16 idx;
e336be
 	u16 tail;
e336be
 	u16 next_to_comp;
e336be
+	u16 llq_last_copy_tail;
e336be
 	u32 tx_max_header_size;
e336be
 	u8 phase;
e336be
 	u8 desc_entry_size;
e336be
@@ -334,6 +369,8 @@ struct ena_com_dev {
e336be
 	u16 intr_delay_resolution;
e336be
 	u32 intr_moder_tx_interval;
e336be
 	struct ena_intr_moder_entry *intr_moder_tbl;
e336be
+
e336be
+	struct ena_com_llq_info llq_info;
e336be
 };
e336be
 
e336be
 struct ena_com_dev_get_features_ctx {
e336be
@@ -342,6 +379,7 @@ struct ena_com_dev_get_features_ctx {
e336be
 	struct ena_admin_feature_aenq_desc aenq;
e336be
 	struct ena_admin_feature_offload_desc offload;
e336be
 	struct ena_admin_ena_hw_hints hw_hints;
e336be
+	struct ena_admin_feature_llq_desc llq;
e336be
 };
e336be
 
e336be
 struct ena_com_create_io_ctx {
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
index 0c9c0d3ce856..789556960b8e 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
@@ -2959,7 +2959,7 @@ static int ena_calc_io_queue_num(struct pci_dev *pdev,
e336be
 
e336be
 	/* In case of LLQ use the llq number in the get feature cmd */
e336be
 	if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
e336be
-		io_sq_num = get_feat_ctx->max_queues.max_llq_num;
e336be
+		io_sq_num = get_feat_ctx->max_queues.max_legacy_llq_num;
e336be
 
e336be
 		if (io_sq_num == 0) {
e336be
 			dev_err(&pdev->dev,
e336be
@@ -2995,7 +2995,7 @@ static void ena_set_push_mode(struct pci_dev *pdev, struct ena_com_dev *ena_dev,
e336be
 	has_mem_bar = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(ENA_MEM_BAR);
e336be
 
e336be
 	/* Enable push mode if device supports LLQ */
e336be
-	if (has_mem_bar && (get_feat_ctx->max_queues.max_llq_num > 0))
e336be
+	if (has_mem_bar && get_feat_ctx->max_queues.max_legacy_llq_num > 0)
e336be
 		ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
e336be
 	else
e336be
 		ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
e336be
@@ -3131,7 +3131,7 @@ static int ena_calc_queue_size(struct pci_dev *pdev,
e336be
 
e336be
 	if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
e336be
 		queue_size = min_t(u32, queue_size,
e336be
-				   get_feat_ctx->max_queues.max_llq_depth);
e336be
+				   get_feat_ctx->max_queues.max_legacy_llq_depth);
e336be
 
e336be
 	queue_size = rounddown_pow_of_two(queue_size);
e336be
 
e336be
-- 
e336be
2.19.1
e336be
e336be
From 8e9ebea20ab8db4f3a993e815e0b6b84ce98bbfb Mon Sep 17 00:00:00 2001
e336be
From: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Date: Thu, 11 Oct 2018 11:26:19 +0300
e336be
Subject: [PATCH 05/16] net: ena: add functions for handling Low Latency Queues
e336be
 in ena_com
e336be
e336be
This patch introduces APIs for detection, initialization, configuration
e336be
and actual usage of low latency queues(LLQ). It extends transmit API with
e336be
creation of LLQ descriptors in device memory (which include host buffers
e336be
descriptors as well as packet header)
e336be
e336be
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Signed-off-by: David S. Miller <davem@davemloft.net>
e336be
---
e336be
 drivers/net/ethernet/amazon/ena/ena_com.c     | 249 +++++++++++++++++-
e336be
 drivers/net/ethernet/amazon/ena/ena_com.h     |  28 ++
e336be
 drivers/net/ethernet/amazon/ena/ena_eth_com.c | 231 ++++++++++++----
e336be
 drivers/net/ethernet/amazon/ena/ena_eth_com.h |  25 +-
e336be
 drivers/net/ethernet/amazon/ena/ena_netdev.c  |  21 +-
e336be
 5 files changed, 474 insertions(+), 80 deletions(-)
e336be
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_com.c b/drivers/net/ethernet/amazon/ena/ena_com.c
e336be
index b6e6a4721931..5220c7578d6b 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_com.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_com.c
e336be
@@ -58,6 +58,8 @@
e336be
 
e336be
 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
e336be
 
e336be
+#define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT	4
e336be
+
e336be
 #define ENA_REGS_ADMIN_INTR_MASK 1
e336be
 
e336be
 #define ENA_POLL_MS	5
e336be
@@ -352,21 +354,48 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
e336be
 						    &io_sq->desc_addr.phys_addr,
e336be
 						    GFP_KERNEL);
e336be
 		}
e336be
-	} else {
e336be
+
e336be
+		if (!io_sq->desc_addr.virt_addr) {
e336be
+			pr_err("memory allocation failed");
e336be
+			return -ENOMEM;
e336be
+		}
e336be
+	}
e336be
+
e336be
+	if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
e336be
+		/* Allocate bounce buffers */
e336be
+		io_sq->bounce_buf_ctrl.buffer_size =
e336be
+			ena_dev->llq_info.desc_list_entry_size;
e336be
+		io_sq->bounce_buf_ctrl.buffers_num =
e336be
+			ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
e336be
+		io_sq->bounce_buf_ctrl.next_to_use = 0;
e336be
+
e336be
+		size = io_sq->bounce_buf_ctrl.buffer_size *
e336be
+			 io_sq->bounce_buf_ctrl.buffers_num;
e336be
+
e336be
 		dev_node = dev_to_node(ena_dev->dmadev);
e336be
 		set_dev_node(ena_dev->dmadev, ctx->numa_node);
e336be
-		io_sq->desc_addr.virt_addr =
e336be
+		io_sq->bounce_buf_ctrl.base_buffer =
e336be
 			devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
e336be
 		set_dev_node(ena_dev->dmadev, dev_node);
e336be
-		if (!io_sq->desc_addr.virt_addr) {
e336be
-			io_sq->desc_addr.virt_addr =
e336be
+		if (!io_sq->bounce_buf_ctrl.base_buffer)
e336be
+			io_sq->bounce_buf_ctrl.base_buffer =
e336be
 				devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
e336be
+
e336be
+		if (!io_sq->bounce_buf_ctrl.base_buffer) {
e336be
+			pr_err("bounce buffer memory allocation failed");
e336be
+			return -ENOMEM;
e336be
 		}
e336be
-	}
e336be
 
e336be
-	if (!io_sq->desc_addr.virt_addr) {
e336be
-		pr_err("memory allocation failed");
e336be
-		return -ENOMEM;
e336be
+		memcpy(&io_sq->llq_info, &ena_dev->llq_info,
e336be
+		       sizeof(io_sq->llq_info));
e336be
+
e336be
+		/* Initiate the first bounce buffer */
e336be
+		io_sq->llq_buf_ctrl.curr_bounce_buf =
e336be
+			ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
e336be
+		memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
e336be
+		       0x0, io_sq->llq_info.desc_list_entry_size);
e336be
+		io_sq->llq_buf_ctrl.descs_left_in_line =
e336be
+			io_sq->llq_info.descs_num_before_header;
e336be
 	}
e336be
 
e336be
 	io_sq->tail = 0;
e336be
@@ -554,6 +583,156 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c
e336be
 	return ret;
e336be
 }
e336be
 
e336be
+/**
e336be
+ * Set the LLQ configurations of the firmware
e336be
+ *
e336be
+ * The driver provides only the enabled feature values to the device,
e336be
+ * which in turn, checks if they are supported.
e336be
+ */
e336be
+static int ena_com_set_llq(struct ena_com_dev *ena_dev)
e336be
+{
e336be
+	struct ena_com_admin_queue *admin_queue;
e336be
+	struct ena_admin_set_feat_cmd cmd;
e336be
+	struct ena_admin_set_feat_resp resp;
e336be
+	struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
e336be
+	int ret;
e336be
+
e336be
+	memset(&cmd, 0x0, sizeof(cmd));
e336be
+	admin_queue = &ena_dev->admin_queue;
e336be
+
e336be
+	cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
e336be
+	cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
e336be
+
e336be
+	cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
e336be
+	cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
e336be
+	cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
e336be
+	cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
e336be
+
e336be
+	ret = ena_com_execute_admin_command(admin_queue,
e336be
+					    (struct ena_admin_aq_entry *)&cmd,
e336be
+					    sizeof(cmd),
e336be
+					    (struct ena_admin_acq_entry *)&resp,
e336be
+					    sizeof(resp));
e336be
+
e336be
+	if (unlikely(ret))
e336be
+		pr_err("Failed to set LLQ configurations: %d\n", ret);
e336be
+
e336be
+	return ret;
e336be
+}
e336be
+
e336be
+static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
e336be
+				   struct ena_admin_feature_llq_desc *llq_features,
e336be
+				   struct ena_llq_configurations *llq_default_cfg)
e336be
+{
e336be
+	struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
e336be
+	u16 supported_feat;
e336be
+	int rc;
e336be
+
e336be
+	memset(llq_info, 0, sizeof(*llq_info));
e336be
+
e336be
+	supported_feat = llq_features->header_location_ctrl_supported;
e336be
+
e336be
+	if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
e336be
+		llq_info->header_location_ctrl =
e336be
+			llq_default_cfg->llq_header_location;
e336be
+	} else {
e336be
+		pr_err("Invalid header location control, supported: 0x%x\n",
e336be
+		       supported_feat);
e336be
+		return -EINVAL;
e336be
+	}
e336be
+
e336be
+	if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
e336be
+		supported_feat = llq_features->descriptors_stride_ctrl_supported;
e336be
+		if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
e336be
+			llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
e336be
+		} else	{
e336be
+			if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
e336be
+				llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
e336be
+			} else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
e336be
+				llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
e336be
+			} else {
e336be
+				pr_err("Invalid desc_stride_ctrl, supported: 0x%x\n",
e336be
+				       supported_feat);
e336be
+				return -EINVAL;
e336be
+			}
e336be
+
e336be
+			pr_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
e336be
+			       llq_default_cfg->llq_stride_ctrl, supported_feat,
e336be
+			       llq_info->desc_stride_ctrl);
e336be
+		}
e336be
+	} else {
e336be
+		llq_info->desc_stride_ctrl = 0;
e336be
+	}
e336be
+
e336be
+	supported_feat = llq_features->entry_size_ctrl_supported;
e336be
+	if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
e336be
+		llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
e336be
+		llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
e336be
+	} else {
e336be
+		if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
e336be
+			llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
e336be
+			llq_info->desc_list_entry_size = 128;
e336be
+		} else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
e336be
+			llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
e336be
+			llq_info->desc_list_entry_size = 192;
e336be
+		} else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
e336be
+			llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
e336be
+			llq_info->desc_list_entry_size = 256;
e336be
+		} else {
e336be
+			pr_err("Invalid entry_size_ctrl, supported: 0x%x\n",
e336be
+			       supported_feat);
e336be
+			return -EINVAL;
e336be
+		}
e336be
+
e336be
+		pr_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
e336be
+		       llq_default_cfg->llq_ring_entry_size, supported_feat,
e336be
+		       llq_info->desc_list_entry_size);
e336be
+	}
e336be
+	if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
e336be
+		/* The desc list entry size should be whole multiply of 8
e336be
+		 * This requirement comes from __iowrite64_copy()
e336be
+		 */
e336be
+		pr_err("illegal entry size %d\n",
e336be
+		       llq_info->desc_list_entry_size);
e336be
+		return -EINVAL;
e336be
+	}
e336be
+
e336be
+	if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
e336be
+		llq_info->descs_per_entry = llq_info->desc_list_entry_size /
e336be
+			sizeof(struct ena_eth_io_tx_desc);
e336be
+	else
e336be
+		llq_info->descs_per_entry = 1;
e336be
+
e336be
+	supported_feat = llq_features->desc_num_before_header_supported;
e336be
+	if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
e336be
+		llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
e336be
+	} else {
e336be
+		if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
e336be
+			llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
e336be
+		} else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
e336be
+			llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
e336be
+		} else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
e336be
+			llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
e336be
+		} else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
e336be
+			llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
e336be
+		} else {
e336be
+			pr_err("Invalid descs_num_before_header, supported: 0x%x\n",
e336be
+			       supported_feat);
e336be
+			return -EINVAL;
e336be
+		}
e336be
+
e336be
+		pr_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
e336be
+		       llq_default_cfg->llq_num_decs_before_header,
e336be
+		       supported_feat, llq_info->descs_num_before_header);
e336be
+	}
e336be
+
e336be
+	rc = ena_com_set_llq(ena_dev);
e336be
+	if (rc)
e336be
+		pr_err("Cannot set LLQ configuration: %d\n", rc);
e336be
+
e336be
+	return 0;
e336be
+}
e336be
+
e336be
 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
e336be
 							struct ena_com_admin_queue *admin_queue)
e336be
 {
e336be
@@ -725,15 +904,17 @@ static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
e336be
 	if (io_sq->desc_addr.virt_addr) {
e336be
 		size = io_sq->desc_entry_size * io_sq->q_depth;
e336be
 
e336be
-		if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
e336be
-			dma_free_coherent(ena_dev->dmadev, size,
e336be
-					  io_sq->desc_addr.virt_addr,
e336be
-					  io_sq->desc_addr.phys_addr);
e336be
-		else
e336be
-			devm_kfree(ena_dev->dmadev, io_sq->desc_addr.virt_addr);
e336be
+		dma_free_coherent(ena_dev->dmadev, size,
e336be
+				  io_sq->desc_addr.virt_addr,
e336be
+				  io_sq->desc_addr.phys_addr);
e336be
 
e336be
 		io_sq->desc_addr.virt_addr = NULL;
e336be
 	}
e336be
+
e336be
+	if (io_sq->bounce_buf_ctrl.base_buffer) {
e336be
+		devm_kfree(ena_dev->dmadev, io_sq->bounce_buf_ctrl.base_buffer);
e336be
+		io_sq->bounce_buf_ctrl.base_buffer = NULL;
e336be
+	}
e336be
 }
e336be
 
e336be
 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
e336be
@@ -1740,6 +1921,15 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
e336be
 	else
e336be
 		return rc;
e336be
 
e336be
+	rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ);
e336be
+	if (!rc)
e336be
+		memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
e336be
+		       sizeof(get_resp.u.llq));
e336be
+	else if (rc == -EOPNOTSUPP)
e336be
+		memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
e336be
+	else
e336be
+		return rc;
e336be
+
e336be
 	return 0;
e336be
 }
e336be
 
e336be
@@ -2708,3 +2898,34 @@ void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
e336be
 	intr_moder_tbl[level].pkts_per_interval;
e336be
 	entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval;
e336be
 }
e336be
+
e336be
+int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
e336be
+			    struct ena_admin_feature_llq_desc *llq_features,
e336be
+			    struct ena_llq_configurations *llq_default_cfg)
e336be
+{
e336be
+	int rc;
e336be
+	int size;
e336be
+
e336be
+	if (!llq_features->max_llq_num) {
e336be
+		ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
e336be
+		return 0;
e336be
+	}
e336be
+
e336be
+	rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
e336be
+	if (rc)
e336be
+		return rc;
e336be
+
e336be
+	/* Validate the descriptor is not too big */
e336be
+	size = ena_dev->tx_max_header_size;
e336be
+	size += ena_dev->llq_info.descs_num_before_header *
e336be
+		sizeof(struct ena_eth_io_tx_desc);
e336be
+
e336be
+	if (unlikely(ena_dev->llq_info.desc_list_entry_size < size)) {
e336be
+		pr_err("the size of the LLQ entry is smaller than needed\n");
e336be
+		return -EINVAL;
e336be
+	}
e336be
+
e336be
+	ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
e336be
+
e336be
+	return 0;
e336be
+}
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_com.h b/drivers/net/ethernet/amazon/ena/ena_com.h
e336be
index 50e6c8f6f138..25af8d025919 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_com.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_com.h
e336be
@@ -37,6 +37,7 @@
e336be
 #include <linux/delay.h>
e336be
 #include <linux/dma-mapping.h>
e336be
 #include <linux/gfp.h>
e336be
+#include <linux/io.h>
e336be
 #include <linux/sched.h>
e336be
 #include <linux/sizes.h>
e336be
 #include <linux/spinlock.h>
e336be
@@ -973,6 +974,16 @@ void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
e336be
 				       enum ena_intr_moder_level level,
e336be
 				       struct ena_intr_moder_entry *entry);
e336be
 
e336be
+/* ena_com_config_dev_mode - Configure the placement policy of the device.
e336be
+ * @ena_dev: ENA communication layer struct
e336be
+ * @llq_features: LLQ feature descriptor, retrieve via
e336be
+ *                ena_com_get_dev_attr_feat.
e336be
+ * @ena_llq_config: The default driver LLQ parameters configurations
e336be
+ */
e336be
+int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
e336be
+			    struct ena_admin_feature_llq_desc *llq_features,
e336be
+			    struct ena_llq_configurations *llq_default_config);
e336be
+
e336be
 static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
e336be
 {
e336be
 	return ena_dev->adaptive_coalescing;
e336be
@@ -1082,4 +1093,21 @@ static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,
e336be
 		intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
e336be
 }
e336be
 
e336be
+static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl)
e336be
+{
e336be
+	u16 size, buffers_num;
e336be
+	u8 *buf;
e336be
+
e336be
+	size = bounce_buf_ctrl->buffer_size;
e336be
+	buffers_num = bounce_buf_ctrl->buffers_num;
e336be
+
e336be
+	buf = bounce_buf_ctrl->base_buffer +
e336be
+		(bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size;
e336be
+
e336be
+	prefetchw(bounce_buf_ctrl->base_buffer +
e336be
+		(bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size);
e336be
+
e336be
+	return buf;
e336be
+}
e336be
+
e336be
 #endif /* !(ENA_COM) */
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_eth_com.c b/drivers/net/ethernet/amazon/ena/ena_eth_com.c
e336be
index 9c0511e9f9a2..17107ca107e3 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_eth_com.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_eth_com.c
e336be
@@ -59,7 +59,7 @@ static inline struct ena_eth_io_rx_cdesc_base *ena_com_get_next_rx_cdesc(
e336be
 	return cdesc;
e336be
 }
e336be
 
e336be
-static inline void *get_sq_desc(struct ena_com_io_sq *io_sq)
e336be
+static inline void *get_sq_desc_regular_queue(struct ena_com_io_sq *io_sq)
e336be
 {
e336be
 	u16 tail_masked;
e336be
 	u32 offset;
e336be
@@ -71,45 +71,159 @@ static inline void *get_sq_desc(struct ena_com_io_sq *io_sq)
e336be
 	return (void *)((uintptr_t)io_sq->desc_addr.virt_addr + offset);
e336be
 }
e336be
 
e336be
-static inline void ena_com_copy_curr_sq_desc_to_dev(struct ena_com_io_sq *io_sq)
e336be
+static inline int ena_com_write_bounce_buffer_to_dev(struct ena_com_io_sq *io_sq,
e336be
+						     u8 *bounce_buffer)
e336be
 {
e336be
-	u16 tail_masked = io_sq->tail & (io_sq->q_depth - 1);
e336be
-	u32 offset = tail_masked * io_sq->desc_entry_size;
e336be
+	struct ena_com_llq_info *llq_info = &io_sq->llq_info;
e336be
 
e336be
-	/* In case this queue isn't a LLQ */
e336be
-	if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
e336be
-		return;
e336be
+	u16 dst_tail_mask;
e336be
+	u32 dst_offset;
e336be
 
e336be
-	memcpy_toio(io_sq->desc_addr.pbuf_dev_addr + offset,
e336be
-		    io_sq->desc_addr.virt_addr + offset,
e336be
-		    io_sq->desc_entry_size);
e336be
-}
e336be
+	dst_tail_mask = io_sq->tail & (io_sq->q_depth - 1);
e336be
+	dst_offset = dst_tail_mask * llq_info->desc_list_entry_size;
e336be
+
e336be
+	/* Make sure everything was written into the bounce buffer before
e336be
+	 * writing the bounce buffer to the device
e336be
+	 */
e336be
+	wmb();
e336be
+
e336be
+	/* The line is completed. Copy it to dev */
e336be
+	__iowrite64_copy(io_sq->desc_addr.pbuf_dev_addr + dst_offset,
e336be
+			 bounce_buffer, (llq_info->desc_list_entry_size) / 8);
e336be
 
e336be
-static inline void ena_com_sq_update_tail(struct ena_com_io_sq *io_sq)
e336be
-{
e336be
 	io_sq->tail++;
e336be
 
e336be
 	/* Switch phase bit in case of wrap around */
e336be
 	if (unlikely((io_sq->tail & (io_sq->q_depth - 1)) == 0))
e336be
 		io_sq->phase ^= 1;
e336be
+
e336be
+	return 0;
e336be
 }
e336be
 
e336be
-static inline int ena_com_write_header(struct ena_com_io_sq *io_sq,
e336be
-				       u8 *head_src, u16 header_len)
e336be
+static inline int ena_com_write_header_to_bounce(struct ena_com_io_sq *io_sq,
e336be
+						 u8 *header_src,
e336be
+						 u16 header_len)
e336be
 {
e336be
-	u16 tail_masked = io_sq->tail & (io_sq->q_depth - 1);
e336be
-	u8 __iomem *dev_head_addr =
e336be
-		io_sq->header_addr + (tail_masked * io_sq->tx_max_header_size);
e336be
+	struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
e336be
+	struct ena_com_llq_info *llq_info = &io_sq->llq_info;
e336be
+	u8 *bounce_buffer = pkt_ctrl->curr_bounce_buf;
e336be
+	u16 header_offset;
e336be
 
e336be
-	if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
e336be
+	if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST))
e336be
 		return 0;
e336be
 
e336be
-	if (unlikely(!io_sq->header_addr)) {
e336be
-		pr_err("Push buffer header ptr is NULL\n");
e336be
-		return -EINVAL;
e336be
+	header_offset =
e336be
+		llq_info->descs_num_before_header * io_sq->desc_entry_size;
e336be
+
e336be
+	if (unlikely((header_offset + header_len) >
e336be
+		     llq_info->desc_list_entry_size)) {
e336be
+		pr_err("trying to write header larger than llq entry can accommodate\n");
e336be
+		return -EFAULT;
e336be
+	}
e336be
+
e336be
+	if (unlikely(!bounce_buffer)) {
e336be
+		pr_err("bounce buffer is NULL\n");
e336be
+		return -EFAULT;
e336be
+	}
e336be
+
e336be
+	memcpy(bounce_buffer + header_offset, header_src, header_len);
e336be
+
e336be
+	return 0;
e336be
+}
e336be
+
e336be
+static inline void *get_sq_desc_llq(struct ena_com_io_sq *io_sq)
e336be
+{
e336be
+	struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
e336be
+	u8 *bounce_buffer;
e336be
+	void *sq_desc;
e336be
+
e336be
+	bounce_buffer = pkt_ctrl->curr_bounce_buf;
e336be
+
e336be
+	if (unlikely(!bounce_buffer)) {
e336be
+		pr_err("bounce buffer is NULL\n");
e336be
+		return NULL;
e336be
+	}
e336be
+
e336be
+	sq_desc = bounce_buffer + pkt_ctrl->idx * io_sq->desc_entry_size;
e336be
+	pkt_ctrl->idx++;
e336be
+	pkt_ctrl->descs_left_in_line--;
e336be
+
e336be
+	return sq_desc;
e336be
+}
e336be
+
e336be
+static inline int ena_com_close_bounce_buffer(struct ena_com_io_sq *io_sq)
e336be
+{
e336be
+	struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
e336be
+	struct ena_com_llq_info *llq_info = &io_sq->llq_info;
e336be
+	int rc;
e336be
+
e336be
+	if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST))
e336be
+		return 0;
e336be
+
e336be
+	/* bounce buffer was used, so write it and get a new one */
e336be
+	if (pkt_ctrl->idx) {
e336be
+		rc = ena_com_write_bounce_buffer_to_dev(io_sq,
e336be
+							pkt_ctrl->curr_bounce_buf);
e336be
+		if (unlikely(rc))
e336be
+			return rc;
e336be
+
e336be
+		pkt_ctrl->curr_bounce_buf =
e336be
+			ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
e336be
+		memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
e336be
+		       0x0, llq_info->desc_list_entry_size);
e336be
+	}
e336be
+
e336be
+	pkt_ctrl->idx = 0;
e336be
+	pkt_ctrl->descs_left_in_line = llq_info->descs_num_before_header;
e336be
+	return 0;
e336be
+}
e336be
+
e336be
+static inline void *get_sq_desc(struct ena_com_io_sq *io_sq)
e336be
+{
e336be
+	if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
e336be
+		return get_sq_desc_llq(io_sq);
e336be
+
e336be
+	return get_sq_desc_regular_queue(io_sq);
e336be
+}
e336be
+
e336be
+static inline int ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq)
e336be
+{
e336be
+	struct ena_com_llq_pkt_ctrl *pkt_ctrl = &io_sq->llq_buf_ctrl;
e336be
+	struct ena_com_llq_info *llq_info = &io_sq->llq_info;
e336be
+	int rc;
e336be
+
e336be
+	if (!pkt_ctrl->descs_left_in_line) {
e336be
+		rc = ena_com_write_bounce_buffer_to_dev(io_sq,
e336be
+							pkt_ctrl->curr_bounce_buf);
e336be
+		if (unlikely(rc))
e336be
+			return rc;
e336be
+
e336be
+		pkt_ctrl->curr_bounce_buf =
e336be
+			ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
e336be
+			memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
e336be
+			       0x0, llq_info->desc_list_entry_size);
e336be
+
e336be
+		pkt_ctrl->idx = 0;
e336be
+		if (unlikely(llq_info->desc_stride_ctrl == ENA_ADMIN_SINGLE_DESC_PER_ENTRY))
e336be
+			pkt_ctrl->descs_left_in_line = 1;
e336be
+		else
e336be
+			pkt_ctrl->descs_left_in_line =
e336be
+			llq_info->desc_list_entry_size / io_sq->desc_entry_size;
e336be
 	}
e336be
 
e336be
-	memcpy_toio(dev_head_addr, head_src, header_len);
e336be
+	return 0;
e336be
+}
e336be
+
e336be
+static inline int ena_com_sq_update_tail(struct ena_com_io_sq *io_sq)
e336be
+{
e336be
+	if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
e336be
+		return ena_com_sq_update_llq_tail(io_sq);
e336be
+
e336be
+	io_sq->tail++;
e336be
+
e336be
+	/* Switch phase bit in case of wrap around */
e336be
+	if (unlikely((io_sq->tail & (io_sq->q_depth - 1)) == 0))
e336be
+		io_sq->phase ^= 1;
e336be
 
e336be
 	return 0;
e336be
 }
e336be
@@ -177,8 +291,8 @@ static inline bool ena_com_meta_desc_changed(struct ena_com_io_sq *io_sq,
e336be
 	return false;
e336be
 }
e336be
 
e336be
-static inline void ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq,
e336be
-							 struct ena_com_tx_ctx *ena_tx_ctx)
e336be
+static inline int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq,
e336be
+							struct ena_com_tx_ctx *ena_tx_ctx)
e336be
 {
e336be
 	struct ena_eth_io_tx_meta_desc *meta_desc = NULL;
e336be
 	struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
e336be
@@ -223,8 +337,7 @@ static inline void ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *i
e336be
 	memcpy(&io_sq->cached_tx_meta, ena_meta,
e336be
 	       sizeof(struct ena_com_tx_meta));
e336be
 
e336be
-	ena_com_copy_curr_sq_desc_to_dev(io_sq);
e336be
-	ena_com_sq_update_tail(io_sq);
e336be
+	return ena_com_sq_update_tail(io_sq);
e336be
 }
e336be
 
e336be
 static inline void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx,
e336be
@@ -262,18 +375,19 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
e336be
 {
e336be
 	struct ena_eth_io_tx_desc *desc = NULL;
e336be
 	struct ena_com_buf *ena_bufs = ena_tx_ctx->ena_bufs;
e336be
-	void *push_header = ena_tx_ctx->push_header;
e336be
+	void *buffer_to_push = ena_tx_ctx->push_header;
e336be
 	u16 header_len = ena_tx_ctx->header_len;
e336be
 	u16 num_bufs = ena_tx_ctx->num_bufs;
e336be
-	int total_desc, i, rc;
e336be
+	u16 start_tail = io_sq->tail;
e336be
+	int i, rc;
e336be
 	bool have_meta;
e336be
 	u64 addr_hi;
e336be
 
e336be
 	WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_TX, "wrong Q type");
e336be
 
e336be
 	/* num_bufs +1 for potential meta desc */
e336be
-	if (ena_com_sq_empty_space(io_sq) < (num_bufs + 1)) {
e336be
-		pr_err("Not enough space in the tx queue\n");
e336be
+	if (unlikely(!ena_com_sq_have_enough_space(io_sq, num_bufs + 1))) {
e336be
+		pr_debug("Not enough space in the tx queue\n");
e336be
 		return -ENOMEM;
e336be
 	}
e336be
 
e336be
@@ -283,23 +397,32 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
e336be
 		return -EINVAL;
e336be
 	}
e336be
 
e336be
-	/* start with pushing the header (if needed) */
e336be
-	rc = ena_com_write_header(io_sq, push_header, header_len);
e336be
+	if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
e336be
+		     !buffer_to_push))
e336be
+		return -EINVAL;
e336be
+
e336be
+	rc = ena_com_write_header_to_bounce(io_sq, buffer_to_push, header_len);
e336be
 	if (unlikely(rc))
e336be
 		return rc;
e336be
 
e336be
 	have_meta = ena_tx_ctx->meta_valid && ena_com_meta_desc_changed(io_sq,
e336be
 			ena_tx_ctx);
e336be
-	if (have_meta)
e336be
-		ena_com_create_and_store_tx_meta_desc(io_sq, ena_tx_ctx);
e336be
+	if (have_meta) {
e336be
+		rc = ena_com_create_and_store_tx_meta_desc(io_sq, ena_tx_ctx);
e336be
+		if (unlikely(rc))
e336be
+			return rc;
e336be
+	}
e336be
 
e336be
-	/* If the caller doesn't want send packets */
e336be
+	/* If the caller doesn't want to send packets */
e336be
 	if (unlikely(!num_bufs && !header_len)) {
e336be
-		*nb_hw_desc = have_meta ? 0 : 1;
e336be
-		return 0;
e336be
+		rc = ena_com_close_bounce_buffer(io_sq);
e336be
+		*nb_hw_desc = io_sq->tail - start_tail;
e336be
+		return rc;
e336be
 	}
e336be
 
e336be
 	desc = get_sq_desc(io_sq);
e336be
+	if (unlikely(!desc))
e336be
+		return -EFAULT;
e336be
 	memset(desc, 0x0, sizeof(struct ena_eth_io_tx_desc));
e336be
 
e336be
 	/* Set first desc when we don't have meta descriptor */
e336be
@@ -351,10 +474,14 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
e336be
 	for (i = 0; i < num_bufs; i++) {
e336be
 		/* The first desc share the same desc as the header */
e336be
 		if (likely(i != 0)) {
e336be
-			ena_com_copy_curr_sq_desc_to_dev(io_sq);
e336be
-			ena_com_sq_update_tail(io_sq);
e336be
+			rc = ena_com_sq_update_tail(io_sq);
e336be
+			if (unlikely(rc))
e336be
+				return rc;
e336be
 
e336be
 			desc = get_sq_desc(io_sq);
e336be
+			if (unlikely(!desc))
e336be
+				return -EFAULT;
e336be
+
e336be
 			memset(desc, 0x0, sizeof(struct ena_eth_io_tx_desc));
e336be
 
e336be
 			desc->len_ctrl |= (io_sq->phase <<
e336be
@@ -377,15 +504,14 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
e336be
 	/* set the last desc indicator */
e336be
 	desc->len_ctrl |= ENA_ETH_IO_TX_DESC_LAST_MASK;
e336be
 
e336be
-	ena_com_copy_curr_sq_desc_to_dev(io_sq);
e336be
-
e336be
-	ena_com_sq_update_tail(io_sq);
e336be
+	rc = ena_com_sq_update_tail(io_sq);
e336be
+	if (unlikely(rc))
e336be
+		return rc;
e336be
 
e336be
-	total_desc = max_t(u16, num_bufs, 1);
e336be
-	total_desc += have_meta ? 1 : 0;
e336be
+	rc = ena_com_close_bounce_buffer(io_sq);
e336be
 
e336be
-	*nb_hw_desc = total_desc;
e336be
-	return 0;
e336be
+	*nb_hw_desc = io_sq->tail - start_tail;
e336be
+	return rc;
e336be
 }
e336be
 
e336be
 int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
e336be
@@ -444,15 +570,18 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
e336be
 
e336be
 	WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX, "wrong Q type");
e336be
 
e336be
-	if (unlikely(ena_com_sq_empty_space(io_sq) == 0))
e336be
+	if (unlikely(!ena_com_sq_have_enough_space(io_sq, 1)))
e336be
 		return -ENOSPC;
e336be
 
e336be
 	desc = get_sq_desc(io_sq);
e336be
+	if (unlikely(!desc))
e336be
+		return -EFAULT;
e336be
+
e336be
 	memset(desc, 0x0, sizeof(struct ena_eth_io_rx_desc));
e336be
 
e336be
 	desc->length = ena_buf->len;
e336be
 
e336be
-	desc->ctrl |= ENA_ETH_IO_RX_DESC_FIRST_MASK;
e336be
+	desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK;
e336be
 	desc->ctrl |= ENA_ETH_IO_RX_DESC_LAST_MASK;
e336be
 	desc->ctrl |= io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK;
e336be
 	desc->ctrl |= ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
e336be
@@ -463,9 +592,7 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
e336be
 	desc->buff_addr_hi =
e336be
 		((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);
e336be
 
e336be
-	ena_com_sq_update_tail(io_sq);
e336be
-
e336be
-	return 0;
e336be
+	return ena_com_sq_update_tail(io_sq);
e336be
 }
e336be
 
e336be
 bool ena_com_cq_empty(struct ena_com_io_cq *io_cq)
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_eth_com.h b/drivers/net/ethernet/amazon/ena/ena_eth_com.h
e336be
index 4930324e9d8d..bcc84072367d 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_eth_com.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_eth_com.h
e336be
@@ -94,7 +94,7 @@ static inline void ena_com_unmask_intr(struct ena_com_io_cq *io_cq,
e336be
 	writel(intr_reg->intr_control, io_cq->unmask_reg);
e336be
 }
e336be
 
e336be
-static inline int ena_com_sq_empty_space(struct ena_com_io_sq *io_sq)
e336be
+static inline int ena_com_free_desc(struct ena_com_io_sq *io_sq)
e336be
 {
e336be
 	u16 tail, next_to_comp, cnt;
e336be
 
e336be
@@ -105,11 +105,28 @@ static inline int ena_com_sq_empty_space(struct ena_com_io_sq *io_sq)
e336be
 	return io_sq->q_depth - 1 - cnt;
e336be
 }
e336be
 
e336be
-static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
e336be
+/* Check if the submission queue has enough space to hold required_buffers */
e336be
+static inline bool ena_com_sq_have_enough_space(struct ena_com_io_sq *io_sq,
e336be
+						u16 required_buffers)
e336be
 {
e336be
-	u16 tail;
e336be
+	int temp;
e336be
 
e336be
-	tail = io_sq->tail;
e336be
+	if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
e336be
+		return ena_com_free_desc(io_sq) >= required_buffers;
e336be
+
e336be
+	/* This calculation doesn't need to be 100% accurate. So to reduce
e336be
+	 * the calculation overhead just Subtract 2 lines from the free descs
e336be
+	 * (one for the header line and one to compensate the devision
e336be
+	 * down calculation.
e336be
+	 */
e336be
+	temp = required_buffers / io_sq->llq_info.descs_per_entry + 2;
e336be
+
e336be
+	return ena_com_free_desc(io_sq) > temp;
e336be
+}
e336be
+
e336be
+static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
e336be
+{
e336be
+	u16 tail = io_sq->tail;
e336be
 
e336be
 	pr_debug("write submission queue doorbell for queue: %d tail: %d\n",
e336be
 		 io_sq->qid, tail);
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
index 789556960b8e..e732bd2ddd32 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
@@ -804,12 +804,13 @@ static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget)
e336be
 	 */
e336be
 	smp_mb();
e336be
 
e336be
-	above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
e336be
-		ENA_TX_WAKEUP_THRESH;
e336be
+	above_thresh = ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
e336be
+						    ENA_TX_WAKEUP_THRESH);
e336be
 	if (unlikely(netif_tx_queue_stopped(txq) && above_thresh)) {
e336be
 		__netif_tx_lock(txq, smp_processor_id());
e336be
-		above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
e336be
-			ENA_TX_WAKEUP_THRESH;
e336be
+		above_thresh =
e336be
+			ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
e336be
+						     ENA_TX_WAKEUP_THRESH);
e336be
 		if (netif_tx_queue_stopped(txq) && above_thresh) {
e336be
 			netif_tx_wake_queue(txq);
e336be
 			u64_stats_update_begin(&tx_ring->syncp);
e336be
@@ -1101,7 +1102,7 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
e336be
 
e336be
 	rx_ring->next_to_clean = next_to_clean;
e336be
 
e336be
-	refill_required = ena_com_sq_empty_space(rx_ring->ena_com_io_sq);
e336be
+	refill_required = ena_com_free_desc(rx_ring->ena_com_io_sq);
e336be
 	refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER;
e336be
 
e336be
 	/* Optimization, try to batch new rx buffers */
e336be
@@ -2115,8 +2116,8 @@ static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
e336be
 	 * to sgl_size + 2. one for the meta descriptor and one for header
e336be
 	 * (if the header is larger than tx_max_header_size).
e336be
 	 */
e336be
-	if (unlikely(ena_com_sq_empty_space(tx_ring->ena_com_io_sq) <
e336be
-		     (tx_ring->sgl_size + 2))) {
e336be
+	if (unlikely(!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
e336be
+						   tx_ring->sgl_size + 2))) {
e336be
 		netif_dbg(adapter, tx_queued, dev, "%s stop queue %d\n",
e336be
 			  __func__, qid);
e336be
 
e336be
@@ -2135,8 +2136,8 @@ static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
e336be
 		 */
e336be
 		smp_mb();
e336be
 
e336be
-		if (ena_com_sq_empty_space(tx_ring->ena_com_io_sq)
e336be
-				> ENA_TX_WAKEUP_THRESH) {
e336be
+		if (ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
e336be
+						 ENA_TX_WAKEUP_THRESH)) {
e336be
 			netif_tx_wake_queue(txq);
e336be
 			u64_stats_update_begin(&tx_ring->syncp);
e336be
 			tx_ring->tx_stats.queue_wakeup++;
e336be
@@ -2813,7 +2814,7 @@ static void check_for_empty_rx_ring(struct ena_adapter *adapter)
e336be
 		rx_ring = &adapter->rx_ring[i];
e336be
 
e336be
 		refill_required =
e336be
-			ena_com_sq_empty_space(rx_ring->ena_com_io_sq);
e336be
+			ena_com_free_desc(rx_ring->ena_com_io_sq);
e336be
 		if (unlikely(refill_required == (rx_ring->ring_size - 1))) {
e336be
 			rx_ring->empty_rx_queue++;
e336be
 
e336be
-- 
e336be
2.19.1
e336be
e336be
From e4729991ed2e7e26e4b061369d7dee054ca4710f Mon Sep 17 00:00:00 2001
e336be
From: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Date: Thu, 11 Oct 2018 11:26:20 +0300
e336be
Subject: [PATCH 06/16] net: ena: add functions for handling Low Latency Queues
e336be
 in ena_netdev
e336be
e336be
This patch includes all code changes necessary in ena_netdev to enable
e336be
packet sending via the LLQ placemnt mode.
e336be
e336be
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Signed-off-by: David S. Miller <davem@davemloft.net>
e336be
---
e336be
 drivers/net/ethernet/amazon/ena/ena_ethtool.c |   1 +
e336be
 drivers/net/ethernet/amazon/ena/ena_netdev.c  | 387 +++++++++++-------
e336be
 drivers/net/ethernet/amazon/ena/ena_netdev.h  |   6 +
e336be
 3 files changed, 251 insertions(+), 143 deletions(-)
e336be
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_ethtool.c b/drivers/net/ethernet/amazon/ena/ena_ethtool.c
e336be
index 521607bc4393..fd28bd0d1c1e 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_ethtool.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_ethtool.c
e336be
@@ -81,6 +81,7 @@ static const struct ena_stats ena_stats_tx_strings[] = {
e336be
 	ENA_STAT_TX_ENTRY(doorbells),
e336be
 	ENA_STAT_TX_ENTRY(prepare_ctx_err),
e336be
 	ENA_STAT_TX_ENTRY(bad_req_id),
e336be
+	ENA_STAT_TX_ENTRY(llq_buffer_copy),
e336be
 	ENA_STAT_TX_ENTRY(missed_tx),
e336be
 };
e336be
 
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
index e732bd2ddd32..fcdfaf0ab8a7 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
@@ -237,6 +237,17 @@ static int ena_setup_tx_resources(struct ena_adapter *adapter, int qid)
e336be
 		}
e336be
 	}
e336be
 
e336be
+	size = tx_ring->tx_max_header_size;
e336be
+	tx_ring->push_buf_intermediate_buf = vzalloc_node(size, node);
e336be
+	if (!tx_ring->push_buf_intermediate_buf) {
e336be
+		tx_ring->push_buf_intermediate_buf = vzalloc(size);
e336be
+		if (!tx_ring->push_buf_intermediate_buf) {
e336be
+			vfree(tx_ring->tx_buffer_info);
e336be
+			vfree(tx_ring->free_tx_ids);
e336be
+			return -ENOMEM;
e336be
+		}
e336be
+	}
e336be
+
e336be
 	/* Req id ring for TX out of order completions */
e336be
 	for (i = 0; i < tx_ring->ring_size; i++)
e336be
 		tx_ring->free_tx_ids[i] = i;
e336be
@@ -265,6 +276,9 @@ static void ena_free_tx_resources(struct ena_adapter *adapter, int qid)
e336be
 
e336be
 	vfree(tx_ring->free_tx_ids);
e336be
 	tx_ring->free_tx_ids = NULL;
e336be
+
e336be
+	vfree(tx_ring->push_buf_intermediate_buf);
e336be
+	tx_ring->push_buf_intermediate_buf = NULL;
e336be
 }
e336be
 
e336be
 /* ena_setup_all_tx_resources - allocate I/O Tx queues resources for All queues
e336be
@@ -602,6 +616,36 @@ static void ena_free_all_rx_bufs(struct ena_adapter *adapter)
e336be
 		ena_free_rx_bufs(adapter, i);
e336be
 }
e336be
 
e336be
+static inline void ena_unmap_tx_skb(struct ena_ring *tx_ring,
e336be
+				    struct ena_tx_buffer *tx_info)
e336be
+{
e336be
+	struct ena_com_buf *ena_buf;
e336be
+	u32 cnt;
e336be
+	int i;
e336be
+
e336be
+	ena_buf = tx_info->bufs;
e336be
+	cnt = tx_info->num_of_bufs;
e336be
+
e336be
+	if (unlikely(!cnt))
e336be
+		return;
e336be
+
e336be
+	if (tx_info->map_linear_data) {
e336be
+		dma_unmap_single(tx_ring->dev,
e336be
+				 dma_unmap_addr(ena_buf, paddr),
e336be
+				 dma_unmap_len(ena_buf, len),
e336be
+				 DMA_TO_DEVICE);
e336be
+		ena_buf++;
e336be
+		cnt--;
e336be
+	}
e336be
+
e336be
+	/* unmap remaining mapped pages */
e336be
+	for (i = 0; i < cnt; i++) {
e336be
+		dma_unmap_page(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
e336be
+			       dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
e336be
+		ena_buf++;
e336be
+	}
e336be
+}
e336be
+
e336be
 /* ena_free_tx_bufs - Free Tx Buffers per Queue
e336be
  * @tx_ring: TX ring for which buffers be freed
e336be
  */
e336be
@@ -612,9 +656,6 @@ static void ena_free_tx_bufs(struct ena_ring *tx_ring)
e336be
 
e336be
 	for (i = 0; i < tx_ring->ring_size; i++) {
e336be
 		struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i];
e336be
-		struct ena_com_buf *ena_buf;
e336be
-		int nr_frags;
e336be
-		int j;
e336be
 
e336be
 		if (!tx_info->skb)
e336be
 			continue;
e336be
@@ -630,21 +671,7 @@ static void ena_free_tx_bufs(struct ena_ring *tx_ring)
e336be
 				   tx_ring->qid, i);
e336be
 		}
e336be
 
e336be
-		ena_buf = tx_info->bufs;
e336be
-		dma_unmap_single(tx_ring->dev,
e336be
-				 ena_buf->paddr,
e336be
-				 ena_buf->len,
e336be
-				 DMA_TO_DEVICE);
e336be
-
e336be
-		/* unmap remaining mapped pages */
e336be
-		nr_frags = tx_info->num_of_bufs - 1;
e336be
-		for (j = 0; j < nr_frags; j++) {
e336be
-			ena_buf++;
e336be
-			dma_unmap_page(tx_ring->dev,
e336be
-				       ena_buf->paddr,
e336be
-				       ena_buf->len,
e336be
-				       DMA_TO_DEVICE);
e336be
-		}
e336be
+		ena_unmap_tx_skb(tx_ring, tx_info);
e336be
 
e336be
 		dev_kfree_skb_any(tx_info->skb);
e336be
 	}
e336be
@@ -735,8 +762,6 @@ static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget)
e336be
 	while (tx_pkts < budget) {
e336be
 		struct ena_tx_buffer *tx_info;
e336be
 		struct sk_buff *skb;
e336be
-		struct ena_com_buf *ena_buf;
e336be
-		int i, nr_frags;
e336be
 
e336be
 		rc = ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq,
e336be
 						&req_id);
e336be
@@ -756,24 +781,7 @@ static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget)
e336be
 		tx_info->skb = NULL;
e336be
 		tx_info->last_jiffies = 0;
e336be
 
e336be
-		if (likely(tx_info->num_of_bufs != 0)) {
e336be
-			ena_buf = tx_info->bufs;
e336be
-
e336be
-			dma_unmap_single(tx_ring->dev,
e336be
-					 dma_unmap_addr(ena_buf, paddr),
e336be
-					 dma_unmap_len(ena_buf, len),
e336be
-					 DMA_TO_DEVICE);
e336be
-
e336be
-			/* unmap remaining mapped pages */
e336be
-			nr_frags = tx_info->num_of_bufs - 1;
e336be
-			for (i = 0; i < nr_frags; i++) {
e336be
-				ena_buf++;
e336be
-				dma_unmap_page(tx_ring->dev,
e336be
-					       dma_unmap_addr(ena_buf, paddr),
e336be
-					       dma_unmap_len(ena_buf, len),
e336be
-					       DMA_TO_DEVICE);
e336be
-			}
e336be
-		}
e336be
+		ena_unmap_tx_skb(tx_ring, tx_info);
e336be
 
e336be
 		netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
e336be
 			  "tx_poll: q %d skb %p completed\n", tx_ring->qid,
e336be
@@ -1300,7 +1308,6 @@ static int ena_enable_msix(struct ena_adapter *adapter, int num_queues)
e336be
 
e336be
 	/* Reserved the max msix vectors we might need */
e336be
 	msix_vecs = ENA_MAX_MSIX_VEC(num_queues);
e336be
-
e336be
 	netif_dbg(adapter, probe, adapter->netdev,
e336be
 		  "trying to enable MSI-X, vectors %d\n", msix_vecs);
e336be
 
e336be
@@ -1591,7 +1598,7 @@ static int ena_up_complete(struct ena_adapter *adapter)
e336be
 
e336be
 static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid)
e336be
 {
e336be
-	struct ena_com_create_io_ctx ctx = { 0 };
e336be
+	struct ena_com_create_io_ctx ctx;
e336be
 	struct ena_com_dev *ena_dev;
e336be
 	struct ena_ring *tx_ring;
e336be
 	u32 msix_vector;
e336be
@@ -1604,6 +1611,8 @@ static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid)
e336be
 	msix_vector = ENA_IO_IRQ_IDX(qid);
e336be
 	ena_qid = ENA_IO_TXQ_IDX(qid);
e336be
 
e336be
+	memset(&ctx, 0x0, sizeof(ctx));
e336be
+
e336be
 	ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
e336be
 	ctx.qid = ena_qid;
e336be
 	ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
e336be
@@ -1657,7 +1666,7 @@ static int ena_create_all_io_tx_queues(struct ena_adapter *adapter)
e336be
 static int ena_create_io_rx_queue(struct ena_adapter *adapter, int qid)
e336be
 {
e336be
 	struct ena_com_dev *ena_dev;
e336be
-	struct ena_com_create_io_ctx ctx = { 0 };
e336be
+	struct ena_com_create_io_ctx ctx;
e336be
 	struct ena_ring *rx_ring;
e336be
 	u32 msix_vector;
e336be
 	u16 ena_qid;
e336be
@@ -1669,6 +1678,8 @@ static int ena_create_io_rx_queue(struct ena_adapter *adapter, int qid)
e336be
 	msix_vector = ENA_IO_IRQ_IDX(qid);
e336be
 	ena_qid = ENA_IO_RXQ_IDX(qid);
e336be
 
e336be
+	memset(&ctx, 0x0, sizeof(ctx));
e336be
+
e336be
 	ctx.qid = ena_qid;
e336be
 	ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
e336be
 	ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
e336be
@@ -1986,73 +1997,70 @@ static int ena_check_and_linearize_skb(struct ena_ring *tx_ring,
e336be
 	return rc;
e336be
 }
e336be
 
e336be
-/* Called with netif_tx_lock. */
e336be
-static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
e336be
+static int ena_tx_map_skb(struct ena_ring *tx_ring,
e336be
+			  struct ena_tx_buffer *tx_info,
e336be
+			  struct sk_buff *skb,
e336be
+			  void **push_hdr,
e336be
+			  u16 *header_len)
e336be
 {
e336be
-	struct ena_adapter *adapter = netdev_priv(dev);
e336be
-	struct ena_tx_buffer *tx_info;
e336be
-	struct ena_com_tx_ctx ena_tx_ctx;
e336be
-	struct ena_ring *tx_ring;
e336be
-	struct netdev_queue *txq;
e336be
+	struct ena_adapter *adapter = tx_ring->adapter;
e336be
 	struct ena_com_buf *ena_buf;
e336be
-	void *push_hdr;
e336be
-	u32 len, last_frag;
e336be
-	u16 next_to_use;
e336be
-	u16 req_id;
e336be
-	u16 push_len;
e336be
-	u16 header_len;
e336be
 	dma_addr_t dma;
e336be
-	int qid, rc, nb_hw_desc;
e336be
-	int i = -1;
e336be
-
e336be
-	netif_dbg(adapter, tx_queued, dev, "%s skb %p\n", __func__, skb);
e336be
-	/*  Determine which tx ring we will be placed on */
e336be
-	qid = skb_get_queue_mapping(skb);
e336be
-	tx_ring = &adapter->tx_ring[qid];
e336be
-	txq = netdev_get_tx_queue(dev, qid);
e336be
-
e336be
-	rc = ena_check_and_linearize_skb(tx_ring, skb);
e336be
-	if (unlikely(rc))
e336be
-		goto error_drop_packet;
e336be
-
e336be
-	skb_tx_timestamp(skb);
e336be
-	len = skb_headlen(skb);
e336be
+	u32 skb_head_len, frag_len, last_frag;
e336be
+	u16 push_len = 0;
e336be
+	u16 delta = 0;
e336be
+	int i = 0;
e336be
 
e336be
-	next_to_use = tx_ring->next_to_use;
e336be
-	req_id = tx_ring->free_tx_ids[next_to_use];
e336be
-	tx_info = &tx_ring->tx_buffer_info[req_id];
e336be
-	tx_info->num_of_bufs = 0;
e336be
-
e336be
-	WARN(tx_info->skb, "SKB isn't NULL req_id %d\n", req_id);
e336be
-	ena_buf = tx_info->bufs;
e336be
+	skb_head_len = skb_headlen(skb);
e336be
 	tx_info->skb = skb;
e336be
+	ena_buf = tx_info->bufs;
e336be
 
e336be
 	if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
e336be
-		/* prepared the push buffer */
e336be
-		push_len = min_t(u32, len, tx_ring->tx_max_header_size);
e336be
-		header_len = push_len;
e336be
-		push_hdr = skb->data;
e336be
+		/* When the device is LLQ mode, the driver will copy
e336be
+		 * the header into the device memory space.
e336be
+		 * the ena_com layer assume the header is in a linear
e336be
+		 * memory space.
e336be
+		 * This assumption might be wrong since part of the header
e336be
+		 * can be in the fragmented buffers.
e336be
+		 * Use skb_header_pointer to make sure the header is in a
e336be
+		 * linear memory space.
e336be
+		 */
e336be
+
e336be
+		push_len = min_t(u32, skb->len, tx_ring->tx_max_header_size);
e336be
+		*push_hdr = skb_header_pointer(skb, 0, push_len,
e336be
+					       tx_ring->push_buf_intermediate_buf);
e336be
+		*header_len = push_len;
e336be
+		if (unlikely(skb->data != *push_hdr)) {
e336be
+			u64_stats_update_begin(&tx_ring->syncp);
e336be
+			tx_ring->tx_stats.llq_buffer_copy++;
e336be
+			u64_stats_update_end(&tx_ring->syncp);
e336be
+
e336be
+			delta = push_len - skb_head_len;
e336be
+		}
e336be
 	} else {
e336be
-		push_len = 0;
e336be
-		header_len = min_t(u32, len, tx_ring->tx_max_header_size);
e336be
-		push_hdr = NULL;
e336be
+		*push_hdr = NULL;
e336be
+		*header_len = min_t(u32, skb_head_len,
e336be
+				    tx_ring->tx_max_header_size);
e336be
 	}
e336be
 
e336be
-	netif_dbg(adapter, tx_queued, dev,
e336be
+	netif_dbg(adapter, tx_queued, adapter->netdev,
e336be
 		  "skb: %p header_buf->vaddr: %p push_len: %d\n", skb,
e336be
-		  push_hdr, push_len);
e336be
+		  *push_hdr, push_len);
e336be
 
e336be
-	if (len > push_len) {
e336be
+	if (skb_head_len > push_len) {
e336be
 		dma = dma_map_single(tx_ring->dev, skb->data + push_len,
e336be
-				     len - push_len, DMA_TO_DEVICE);
e336be
-		if (dma_mapping_error(tx_ring->dev, dma))
e336be
+				     skb_head_len - push_len, DMA_TO_DEVICE);
e336be
+		if (unlikely(dma_mapping_error(tx_ring->dev, dma)))
e336be
 			goto error_report_dma_error;
e336be
 
e336be
 		ena_buf->paddr = dma;
e336be
-		ena_buf->len = len - push_len;
e336be
+		ena_buf->len = skb_head_len - push_len;
e336be
 
e336be
 		ena_buf++;
e336be
 		tx_info->num_of_bufs++;
e336be
+		tx_info->map_linear_data = 1;
e336be
+	} else {
e336be
+		tx_info->map_linear_data = 0;
e336be
 	}
e336be
 
e336be
 	last_frag = skb_shinfo(skb)->nr_frags;
e336be
@@ -2060,18 +2068,75 @@ static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
e336be
 	for (i = 0; i < last_frag; i++) {
e336be
 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
e336be
 
e336be
-		len = skb_frag_size(frag);
e336be
-		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len,
e336be
-				       DMA_TO_DEVICE);
e336be
-		if (dma_mapping_error(tx_ring->dev, dma))
e336be
+		frag_len = skb_frag_size(frag);
e336be
+
e336be
+		if (unlikely(delta >= frag_len)) {
e336be
+			delta -= frag_len;
e336be
+			continue;
e336be
+		}
e336be
+
e336be
+		dma = skb_frag_dma_map(tx_ring->dev, frag, delta,
e336be
+				       frag_len - delta, DMA_TO_DEVICE);
e336be
+		if (unlikely(dma_mapping_error(tx_ring->dev, dma)))
e336be
 			goto error_report_dma_error;
e336be
 
e336be
 		ena_buf->paddr = dma;
e336be
-		ena_buf->len = len;
e336be
+		ena_buf->len = frag_len - delta;
e336be
 		ena_buf++;
e336be
+		tx_info->num_of_bufs++;
e336be
+		delta = 0;
e336be
 	}
e336be
 
e336be
-	tx_info->num_of_bufs += last_frag;
e336be
+	return 0;
e336be
+
e336be
+error_report_dma_error:
e336be
+	u64_stats_update_begin(&tx_ring->syncp);
e336be
+	tx_ring->tx_stats.dma_mapping_err++;
e336be
+	u64_stats_update_end(&tx_ring->syncp);
e336be
+	netdev_warn(adapter->netdev, "failed to map skb\n");
e336be
+
e336be
+	tx_info->skb = NULL;
e336be
+
e336be
+	tx_info->num_of_bufs += i;
e336be
+	ena_unmap_tx_skb(tx_ring, tx_info);
e336be
+
e336be
+	return -EINVAL;
e336be
+}
e336be
+
e336be
+/* Called with netif_tx_lock. */
e336be
+static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
e336be
+{
e336be
+	struct ena_adapter *adapter = netdev_priv(dev);
e336be
+	struct ena_tx_buffer *tx_info;
e336be
+	struct ena_com_tx_ctx ena_tx_ctx;
e336be
+	struct ena_ring *tx_ring;
e336be
+	struct netdev_queue *txq;
e336be
+	void *push_hdr;
e336be
+	u16 next_to_use, req_id, header_len;
e336be
+	int qid, rc, nb_hw_desc;
e336be
+
e336be
+	netif_dbg(adapter, tx_queued, dev, "%s skb %p\n", __func__, skb);
e336be
+	/*  Determine which tx ring we will be placed on */
e336be
+	qid = skb_get_queue_mapping(skb);
e336be
+	tx_ring = &adapter->tx_ring[qid];
e336be
+	txq = netdev_get_tx_queue(dev, qid);
e336be
+
e336be
+	rc = ena_check_and_linearize_skb(tx_ring, skb);
e336be
+	if (unlikely(rc))
e336be
+		goto error_drop_packet;
e336be
+
e336be
+	skb_tx_timestamp(skb);
e336be
+
e336be
+	next_to_use = tx_ring->next_to_use;
e336be
+	req_id = tx_ring->free_tx_ids[next_to_use];
e336be
+	tx_info = &tx_ring->tx_buffer_info[req_id];
e336be
+	tx_info->num_of_bufs = 0;
e336be
+
e336be
+	WARN(tx_info->skb, "SKB isn't NULL req_id %d\n", req_id);
e336be
+
e336be
+	rc = ena_tx_map_skb(tx_ring, tx_info, skb, &push_hdr, &header_len);
e336be
+	if (unlikely(rc))
e336be
+		goto error_drop_packet;
e336be
 
e336be
 	memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
e336be
 	ena_tx_ctx.ena_bufs = tx_info->bufs;
e336be
@@ -2087,14 +2152,22 @@ static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
e336be
 	rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
e336be
 				&nb_hw_desc);
e336be
 
e336be
+	/* ena_com_prepare_tx() can't fail due to overflow of tx queue,
e336be
+	 * since the number of free descriptors in the queue is checked
e336be
+	 * after sending the previous packet. In case there isn't enough
e336be
+	 * space in the queue for the next packet, it is stopped
e336be
+	 * until there is again enough available space in the queue.
e336be
+	 * All other failure reasons of ena_com_prepare_tx() are fatal
e336be
+	 * and therefore require a device reset.
e336be
+	 */
e336be
 	if (unlikely(rc)) {
e336be
 		netif_err(adapter, tx_queued, dev,
e336be
 			  "failed to prepare tx bufs\n");
e336be
 		u64_stats_update_begin(&tx_ring->syncp);
e336be
-		tx_ring->tx_stats.queue_stop++;
e336be
 		tx_ring->tx_stats.prepare_ctx_err++;
e336be
 		u64_stats_update_end(&tx_ring->syncp);
e336be
-		netif_tx_stop_queue(txq);
e336be
+		adapter->reset_reason = ENA_REGS_RESET_DRIVER_INVALID_STATE;
e336be
+		set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
e336be
 		goto error_unmap_dma;
e336be
 	}
e336be
 
e336be
@@ -2157,35 +2230,11 @@ static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
e336be
 
e336be
 	return NETDEV_TX_OK;
e336be
 
e336be
-error_report_dma_error:
e336be
-	u64_stats_update_begin(&tx_ring->syncp);
e336be
-	tx_ring->tx_stats.dma_mapping_err++;
e336be
-	u64_stats_update_end(&tx_ring->syncp);
e336be
-	netdev_warn(adapter->netdev, "failed to map skb\n");
e336be
-
e336be
-	tx_info->skb = NULL;
e336be
-
e336be
 error_unmap_dma:
e336be
-	if (i >= 0) {
e336be
-		/* save value of frag that failed */
e336be
-		last_frag = i;
e336be
-
e336be
-		/* start back at beginning and unmap skb */
e336be
-		tx_info->skb = NULL;
e336be
-		ena_buf = tx_info->bufs;
e336be
-		dma_unmap_single(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
e336be
-				 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
e336be
-
e336be
-		/* unmap remaining mapped pages */
e336be
-		for (i = 0; i < last_frag; i++) {
e336be
-			ena_buf++;
e336be
-			dma_unmap_page(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
e336be
-				       dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
e336be
-		}
e336be
-	}
e336be
+	ena_unmap_tx_skb(tx_ring, tx_info);
e336be
+	tx_info->skb = NULL;
e336be
 
e336be
 error_drop_packet:
e336be
-
e336be
 	dev_kfree_skb(skb);
e336be
 	return NETDEV_TX_OK;
e336be
 }
e336be
@@ -2621,7 +2670,9 @@ static int ena_restore_device(struct ena_adapter *adapter)
11f5cb
 		netif_carrier_on(adapter->netdev);
e336be
 
e336be
 	mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
e336be
-	dev_err(&pdev->dev, "Device reset completed successfully\n");
e336be
+	dev_err(&pdev->dev,
e336be
+		"Device reset completed successfully, Driver info: %s\n",
e336be
+		version);
e336be
 
e336be
 	return rc;
e336be
 err_disable_msix:
e336be
@@ -2988,18 +3039,52 @@ static int ena_calc_io_queue_num(struct pci_dev *pdev,
e336be
 	return io_queue_num;
e336be
 }
e336be
 
e336be
-static void ena_set_push_mode(struct pci_dev *pdev, struct ena_com_dev *ena_dev,
e336be
-			      struct ena_com_dev_get_features_ctx *get_feat_ctx)
e336be
+static int ena_set_queues_placement_policy(struct pci_dev *pdev,
e336be
+					   struct ena_com_dev *ena_dev,
e336be
+					   struct ena_admin_feature_llq_desc *llq,
e336be
+					   struct ena_llq_configurations *llq_default_configurations)
e336be
 {
e336be
 	bool has_mem_bar;
e336be
+	int rc;
e336be
+	u32 llq_feature_mask;
e336be
+
e336be
+	llq_feature_mask = 1 << ENA_ADMIN_LLQ;
e336be
+	if (!(ena_dev->supported_features & llq_feature_mask)) {
e336be
+		dev_err(&pdev->dev,
e336be
+			"LLQ is not supported Fallback to host mode policy.\n");
e336be
+		ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
e336be
+		return 0;
e336be
+	}
e336be
 
e336be
 	has_mem_bar = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(ENA_MEM_BAR);
e336be
 
e336be
-	/* Enable push mode if device supports LLQ */
e336be
-	if (has_mem_bar && get_feat_ctx->max_queues.max_legacy_llq_num > 0)
e336be
-		ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
e336be
-	else
e336be
+	rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
e336be
+	if (unlikely(rc)) {
e336be
+		dev_err(&pdev->dev,
e336be
+			"Failed to configure the device mode.  Fallback to host mode policy.\n");
e336be
+		ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
e336be
+		return 0;
e336be
+	}
e336be
+
e336be
+	/* Nothing to config, exit */
e336be
+	if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
e336be
+		return 0;
e336be
+
e336be
+	if (!has_mem_bar) {
e336be
+		dev_err(&pdev->dev,
e336be
+			"ENA device does not expose LLQ bar. Fallback to host mode policy.\n");
e336be
 		ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
e336be
+		return 0;
e336be
+	}
e336be
+
e336be
+	ena_dev->mem_bar = devm_ioremap_wc(&pdev->dev,
e336be
+					   pci_resource_start(pdev, ENA_MEM_BAR),
e336be
+					   pci_resource_len(pdev, ENA_MEM_BAR));
e336be
+
e336be
+	if (!ena_dev->mem_bar)
e336be
+		return -EFAULT;
e336be
+
e336be
+	return 0;
e336be
 }
e336be
 
e336be
 static void ena_set_dev_offloads(struct ena_com_dev_get_features_ctx *feat,
e336be
@@ -3117,6 +3202,15 @@ static void ena_release_bars(struct ena_com_dev *ena_dev, struct pci_dev *pdev)
e336be
 	pci_release_selected_regions(pdev, release_bars);
e336be
 }
e336be
 
e336be
+static inline void set_default_llq_configurations(struct ena_llq_configurations *llq_config)
e336be
+{
e336be
+	llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
e336be
+	llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
e336be
+	llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
e336be
+	llq_config->llq_num_decs_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
e336be
+	llq_config->llq_ring_entry_size_value = 128;
e336be
+}
e336be
+
e336be
 static int ena_calc_queue_size(struct pci_dev *pdev,
e336be
 			       struct ena_com_dev *ena_dev,
e336be
 			       u16 *max_tx_sgl_size,
e336be
@@ -3165,7 +3259,9 @@ static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
e336be
 	static int version_printed;
e336be
 	struct net_device *netdev;
e336be
 	struct ena_adapter *adapter;
e336be
+	struct ena_llq_configurations llq_config;
e336be
 	struct ena_com_dev *ena_dev = NULL;
e336be
+	char *queue_type_str;
e336be
 	static int adapters_found;
e336be
 	int io_queue_num, bars, rc;
e336be
 	int queue_size;
e336be
@@ -3219,16 +3315,13 @@ static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
e336be
 		goto err_free_region;
e336be
 	}
e336be
 
e336be
-	ena_set_push_mode(pdev, ena_dev, &get_feat_ctx);
e336be
+	set_default_llq_configurations(&llq_config);
e336be
 
e336be
-	if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
e336be
-		ena_dev->mem_bar = devm_ioremap_wc(&pdev->dev,
e336be
-						   pci_resource_start(pdev, ENA_MEM_BAR),
e336be
-						   pci_resource_len(pdev, ENA_MEM_BAR));
e336be
-		if (!ena_dev->mem_bar) {
e336be
-			rc = -EFAULT;
e336be
-			goto err_device_destroy;
e336be
-		}
e336be
+	rc = ena_set_queues_placement_policy(pdev, ena_dev, &get_feat_ctx.llq,
e336be
+					     &llq_config);
e336be
+	if (rc) {
e336be
+		dev_err(&pdev->dev, "ena device init failed\n");
e336be
+		goto err_device_destroy;
e336be
 	}
e336be
 
e336be
 	/* initial Tx interrupt delay, Assumes 1 usec granularity.
e336be
@@ -3243,8 +3336,10 @@ static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
e336be
 		goto err_device_destroy;
e336be
 	}
e336be
 
e336be
-	dev_info(&pdev->dev, "creating %d io queues. queue size: %d\n",
e336be
-		 io_queue_num, queue_size);
e336be
+	dev_info(&pdev->dev, "creating %d io queues. queue size: %d. LLQ is %s\n",
e336be
+		 io_queue_num, queue_size,
e336be
+		 (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) ?
e336be
+		 "ENABLED" : "DISABLED");
e336be
 
e336be
 	/* dev zeroed in init_etherdev */
e336be
 	netdev = alloc_etherdev_mq(sizeof(struct ena_adapter), io_queue_num);
e336be
@@ -3334,9 +3429,15 @@ static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
e336be
 	timer_setup(&adapter->timer_service, ena_timer_service, 0);
e336be
 	mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
e336be
 
e336be
-	dev_info(&pdev->dev, "%s found at mem %lx, mac addr %pM Queues %d\n",
e336be
+	if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
e336be
+		queue_type_str = "Regular";
e336be
+	else
e336be
+		queue_type_str = "Low Latency";
e336be
+
e336be
+	dev_info(&pdev->dev,
e336be
+		 "%s found at mem %lx, mac addr %pM Queues %d, Placement policy: %s\n",
e336be
 		 DEVICE_NAME, (long)pci_resource_start(pdev, 0),
e336be
-		 netdev->dev_addr, io_queue_num);
e336be
+		 netdev->dev_addr, io_queue_num, queue_type_str);
e336be
 
e336be
 	set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
e336be
 
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.h b/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
index 7c7ae56c52cf..4fa7d2fda475 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
@@ -151,6 +151,9 @@ struct ena_tx_buffer {
e336be
 	/* num of buffers used by this skb */
e336be
 	u32 num_of_bufs;
e336be
 
e336be
+	/* Indicate if bufs[0] map the linear data of the skb. */
e336be
+	u8 map_linear_data;
e336be
+
e336be
 	/* Used for detect missing tx packets to limit the number of prints */
e336be
 	u32 print_once;
e336be
 	/* Save the last jiffies to detect missing tx packets
e336be
@@ -186,6 +189,7 @@ struct ena_stats_tx {
e336be
 	u64 tx_poll;
e336be
 	u64 doorbells;
e336be
 	u64 bad_req_id;
e336be
+	u64 llq_buffer_copy;
e336be
 	u64 missed_tx;
e336be
 };
e336be
 
e336be
@@ -257,6 +261,8 @@ struct ena_ring {
e336be
 		struct ena_stats_tx tx_stats;
e336be
 		struct ena_stats_rx rx_stats;
e336be
 	};
e336be
+
e336be
+	u8 *push_buf_intermediate_buf;
e336be
 	int empty_rx_queue;
e336be
 } ____cacheline_aligned;
e336be
 
e336be
-- 
e336be
2.19.1
e336be
e336be
From 910193b2d74a25d62354ab63115cd9a28ece1add Mon Sep 17 00:00:00 2001
e336be
From: Peter Robinson <pbrobinson@gmail.com>
e336be
Date: Fri, 23 Nov 2018 12:33:42 +0000
e336be
Subject: [PATCH 07/16] net: ena: use CSUM_CHECKED device indication to report
e336be
 skb's checksum  status
e336be
e336be
Set skb->ip_summed to the correct value as reported by the device.
e336be
Add counter for the case where rx csum offload is enabled but
e336be
device didn't check it.
e336be
e336be
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Signed-off-by: David S. Miller <davem@davemloft.net>
e336be
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
e336be
---
e336be
 drivers/net/ethernet/amazon/ena/ena_eth_com.c     |  3 +++
e336be
 drivers/net/ethernet/amazon/ena/ena_eth_com.h     |  1 +
e336be
 drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h | 10 ++++++++--
e336be
 drivers/net/ethernet/amazon/ena/ena_ethtool.c     |  1 +
e336be
 drivers/net/ethernet/amazon/ena/ena_netdev.c      | 13 ++++++++++++-
e336be
 drivers/net/ethernet/amazon/ena/ena_netdev.h      |  1 +
e336be
 6 files changed, 26 insertions(+), 3 deletions(-)
e336be
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_eth_com.c b/drivers/net/ethernet/amazon/ena/ena_eth_com.c
e336be
index 17107ca107e3..f6c2d3855be8 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_eth_com.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_eth_com.c
e336be
@@ -354,6 +354,9 @@ static inline void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx,
e336be
 	ena_rx_ctx->l4_csum_err =
e336be
 		!!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >>
e336be
 		ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT);
e336be
+	ena_rx_ctx->l4_csum_checked =
e336be
+		!!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >>
e336be
+		ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT);
e336be
 	ena_rx_ctx->hash = cdesc->hash;
e336be
 	ena_rx_ctx->frag =
e336be
 		(cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >>
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_eth_com.h b/drivers/net/ethernet/amazon/ena/ena_eth_com.h
e336be
index bcc84072367d..340d02b64ca6 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_eth_com.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_eth_com.h
e336be
@@ -67,6 +67,7 @@ struct ena_com_rx_ctx {
e336be
 	enum ena_eth_io_l4_proto_index l4_proto;
e336be
 	bool l3_csum_err;
e336be
 	bool l4_csum_err;
e336be
+	u8 l4_csum_checked;
e336be
 	/* fragmented packet */
e336be
 	bool frag;
e336be
 	u32 hash;
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h b/drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h
e336be
index f320c58793a5..4c5ccaa13c42 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h
e336be
@@ -242,9 +242,13 @@ struct ena_eth_io_rx_cdesc_base {
e336be
 	 *    checksum error detected, or, the controller didn't
e336be
 	 *    validate the checksum. This bit is valid only when
e336be
 	 *    l4_proto_idx indicates TCP/UDP packet, and,
e336be
-	 *    ipv4_frag is not set
e336be
+	 *    ipv4_frag is not set. This bit is valid only when
e336be
+	 *    l4_csum_checked below is set.
e336be
 	 * 15 : ipv4_frag - Indicates IPv4 fragmented packet
e336be
-	 * 23:16 : reserved16
e336be
+	 * 16 : l4_csum_checked - L4 checksum was verified
e336be
+	 *    (could be OK or error), when cleared the status of
e336be
+	 *    checksum is unknown
e336be
+	 * 23:17 : reserved17 - MBZ
e336be
 	 * 24 : phase
e336be
 	 * 25 : l3_csum2 - second checksum engine result
e336be
 	 * 26 : first - Indicates first descriptor in
e336be
@@ -390,6 +394,8 @@ struct ena_eth_io_numa_node_cfg_reg {
e336be
 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
e336be
 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
e336be
 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16)
e336be
 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
e336be
 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
e336be
 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_ethtool.c b/drivers/net/ethernet/amazon/ena/ena_ethtool.c
e336be
index fd28bd0d1c1e..f3a5a384e6e8 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_ethtool.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_ethtool.c
e336be
@@ -97,6 +97,7 @@ static const struct ena_stats ena_stats_rx_strings[] = {
e336be
 	ENA_STAT_RX_ENTRY(rx_copybreak_pkt),
e336be
 	ENA_STAT_RX_ENTRY(bad_req_id),
e336be
 	ENA_STAT_RX_ENTRY(empty_rx_ring),
e336be
+	ENA_STAT_RX_ENTRY(csum_unchecked),
e336be
 };
e336be
 
e336be
 static const struct ena_stats ena_stats_ena_com_strings[] = {
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
index fcdfaf0ab8a7..35b0ce5db24b 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
@@ -994,8 +994,19 @@ static inline void ena_rx_checksum(struct ena_ring *rx_ring,
e336be
 			return;
e336be
 		}
e336be
 
e336be
-		skb->ip_summed = CHECKSUM_UNNECESSARY;
e336be
+		if (likely(ena_rx_ctx->l4_csum_checked)) {
e336be
+			skb->ip_summed = CHECKSUM_UNNECESSARY;
e336be
+		} else {
e336be
+			u64_stats_update_begin(&rx_ring->syncp);
e336be
+			rx_ring->rx_stats.csum_unchecked++;
e336be
+			u64_stats_update_end(&rx_ring->syncp);
e336be
+			skb->ip_summed = CHECKSUM_NONE;
e336be
+		}
e336be
+	} else {
e336be
+		skb->ip_summed = CHECKSUM_NONE;
e336be
+		return;
e336be
 	}
e336be
+
e336be
 }
e336be
 
e336be
 static void ena_set_rx_hash(struct ena_ring *rx_ring,
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.h b/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
index 4fa7d2fda475..2d62e2c7fed7 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
@@ -205,6 +205,7 @@ struct ena_stats_rx {
e336be
 	u64 rx_copybreak_pkt;
e336be
 	u64 bad_req_id;
e336be
 	u64 empty_rx_ring;
e336be
+	u64 csum_unchecked;
e336be
 };
e336be
 
e336be
 struct ena_ring {
e336be
-- 
e336be
2.19.1
e336be
e336be
From 20ba28b24e1d861ee3d8757fcadee46f742f29c5 Mon Sep 17 00:00:00 2001
e336be
From: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Date: Thu, 11 Oct 2018 11:26:22 +0300
e336be
Subject: [PATCH 08/16] net: ena: explicit casting and initialization, and
e336be
 clearer error handling
e336be
e336be
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Signed-off-by: David S. Miller <davem@davemloft.net>
e336be
---
e336be
 drivers/net/ethernet/amazon/ena/ena_com.c    | 39 ++++++++++++--------
e336be
 drivers/net/ethernet/amazon/ena/ena_netdev.c |  5 +--
e336be
 drivers/net/ethernet/amazon/ena/ena_netdev.h | 22 +++++------
e336be
 3 files changed, 36 insertions(+), 30 deletions(-)
e336be
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_com.c b/drivers/net/ethernet/amazon/ena/ena_com.c
e336be
index 5220c7578d6b..5c468b28723b 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_com.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_com.c
e336be
@@ -235,7 +235,7 @@ static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queu
e336be
 	tail_masked = admin_queue->sq.tail & queue_size_mask;
e336be
 
e336be
 	/* In case of queue FULL */
e336be
-	cnt = atomic_read(&admin_queue->outstanding_cmds);
e336be
+	cnt = (u16)atomic_read(&admin_queue->outstanding_cmds);
e336be
 	if (cnt >= admin_queue->q_depth) {
e336be
 		pr_debug("admin queue is full.\n");
e336be
 		admin_queue->stats.out_of_space++;
e336be
@@ -304,7 +304,7 @@ static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue
e336be
 						     struct ena_admin_acq_entry *comp,
e336be
 						     size_t comp_size_in_bytes)
e336be
 {
e336be
-	unsigned long flags;
e336be
+	unsigned long flags = 0;
e336be
 	struct ena_comp_ctx *comp_ctx;
e336be
 
e336be
 	spin_lock_irqsave(&admin_queue->q_lock, flags);
e336be
@@ -332,7 +332,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
e336be
 
e336be
 	memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
e336be
 
e336be
-	io_sq->dma_addr_bits = ena_dev->dma_addr_bits;
e336be
+	io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
e336be
 	io_sq->desc_entry_size =
e336be
 		(io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
e336be
 		sizeof(struct ena_eth_io_tx_desc) :
e336be
@@ -486,7 +486,7 @@ static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_qu
e336be
 
e336be
 	/* Go over all the completions */
e336be
 	while ((READ_ONCE(cqe->acq_common_descriptor.flags) &
e336be
-			ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
e336be
+		ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
e336be
 		/* Do not read the rest of the completion entry before the
e336be
 		 * phase bit was validated
e336be
 		 */
e336be
@@ -537,7 +537,8 @@ static int ena_com_comp_status_to_errno(u8 comp_status)
e336be
 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
e336be
 						     struct ena_com_admin_queue *admin_queue)
e336be
 {
e336be
-	unsigned long flags, timeout;
e336be
+	unsigned long flags = 0;
e336be
+	unsigned long timeout;
e336be
 	int ret;
e336be
 
e336be
 	timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout);
e336be
@@ -736,7 +737,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
e336be
 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
e336be
 							struct ena_com_admin_queue *admin_queue)
e336be
 {
e336be
-	unsigned long flags;
e336be
+	unsigned long flags = 0;
e336be
 	int ret;
e336be
 
e336be
 	wait_for_completion_timeout(&comp_ctx->wait_event,
e336be
@@ -782,7 +783,7 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
e336be
 	volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
e336be
 		mmio_read->read_resp;
e336be
 	u32 mmio_read_reg, ret, i;
e336be
-	unsigned long flags;
e336be
+	unsigned long flags = 0;
e336be
 	u32 timeout = mmio_read->reg_read_to;
e336be
 
e336be
 	might_sleep();
e336be
@@ -1426,7 +1427,7 @@ void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
e336be
 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
e336be
 {
e336be
 	struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
e336be
-	unsigned long flags;
e336be
+	unsigned long flags = 0;
e336be
 
e336be
 	spin_lock_irqsave(&admin_queue->q_lock, flags);
e336be
 	while (atomic_read(&admin_queue->outstanding_cmds) != 0) {
e336be
@@ -1470,7 +1471,7 @@ bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
e336be
 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
e336be
 {
e336be
 	struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
e336be
-	unsigned long flags;
e336be
+	unsigned long flags = 0;
e336be
 
e336be
 	spin_lock_irqsave(&admin_queue->q_lock, flags);
e336be
 	ena_dev->admin_queue.running_state = state;
e336be
@@ -1504,7 +1505,7 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
e336be
 	}
e336be
 
e336be
 	if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
e336be
-		pr_warn("Trying to set unsupported aenq events. supported flag: %x asked flag: %x\n",
e336be
+		pr_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
e336be
 			get_resp.u.aenq.supported_groups, groups_flag);
e336be
 		return -EOPNOTSUPP;
e336be
 	}
e336be
@@ -1652,7 +1653,7 @@ int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
e336be
 				    sizeof(*mmio_read->read_resp),
e336be
 				    &mmio_read->read_resp_dma_addr, GFP_KERNEL);
e336be
 	if (unlikely(!mmio_read->read_resp))
e336be
-		return -ENOMEM;
e336be
+		goto err;
e336be
 
e336be
 	ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
e336be
 
e336be
@@ -1661,6 +1662,10 @@ int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
e336be
 	mmio_read->readless_supported = true;
e336be
 
e336be
 	return 0;
e336be
+
e336be
+err:
e336be
+
e336be
+	return -ENOMEM;
e336be
 }
e336be
 
e336be
 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
e336be
@@ -1961,6 +1966,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
e336be
 	struct ena_admin_aenq_entry *aenq_e;
e336be
 	struct ena_admin_aenq_common_desc *aenq_common;
e336be
 	struct ena_com_aenq *aenq  = &dev->aenq;
e336be
+	unsigned long long timestamp;
e336be
 	ena_aenq_handler handler_cb;
e336be
 	u16 masked_head, processed = 0;
e336be
 	u8 phase;
e336be
@@ -1978,10 +1984,11 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
e336be
 		 */
e336be
 		dma_rmb();
e336be
 
e336be
+		timestamp =
e336be
+			(unsigned long long)aenq_common->timestamp_low |
e336be
+			((unsigned long long)aenq_common->timestamp_high << 32);
e336be
 		pr_debug("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n",
e336be
-			 aenq_common->group, aenq_common->syndrom,
e336be
-			 (u64)aenq_common->timestamp_low +
e336be
-				 ((u64)aenq_common->timestamp_high << 32));
e336be
+			 aenq_common->group, aenq_common->syndrom, timestamp);
e336be
 
e336be
 		/* Handle specific event*/
e336be
 		handler_cb = ena_com_get_specific_aenq_cb(dev,
e336be
@@ -2623,8 +2630,8 @@ int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
e336be
 	if (unlikely(!host_attr->host_info))
e336be
 		return -ENOMEM;
e336be
 
e336be
-	host_attr->host_info->ena_spec_version =
e336be
-		((ENA_COMMON_SPEC_VERSION_MAJOR << ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
e336be
+	host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
e336be
+		ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
e336be
 		(ENA_COMMON_SPEC_VERSION_MINOR));
e336be
 
e336be
 	return 0;
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
index 35b0ce5db24b..e345220b4d9a 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
@@ -2604,15 +2604,14 @@ static void ena_destroy_device(struct ena_adapter *adapter, bool graceful)
e336be
 
e336be
 	dev_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags);
e336be
 	adapter->dev_up_before_reset = dev_up;
e336be
-
e336be
 	if (!graceful)
e336be
 		ena_com_set_admin_running_state(ena_dev, false);
e336be
 
e336be
 	if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
e336be
 		ena_down(adapter);
e336be
 
e336be
-	/* Before releasing the ENA resources, a device reset is required.
e336be
-	 * (to prevent the device from accessing them).
e336be
+	/* Stop the device from sending AENQ events (in case reset flag is set
e336be
+	 *  and device is up, ena_close already reset the device
e336be
 	 * In case the reset flag is set and the device is up, ena_down()
e336be
 	 * already perform the reset, so it can be skipped.
e336be
 	 */
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.h b/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
index 2d62e2c7fed7..a16baf0124d5 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
@@ -61,6 +61,17 @@
e336be
 #define ENA_ADMIN_MSIX_VEC		1
e336be
 #define ENA_MAX_MSIX_VEC(io_queues)	(ENA_ADMIN_MSIX_VEC + (io_queues))
e336be
 
e336be
+/* The ENA buffer length fields is 16 bit long. So when PAGE_SIZE == 64kB the
e336be
+ * driver passes 0.
e336be
+ * Since the max packet size the ENA handles is ~9kB limit the buffer length to
e336be
+ * 16kB.
e336be
+ */
e336be
+#if PAGE_SIZE > SZ_16K
e336be
+#define ENA_PAGE_SIZE SZ_16K
e336be
+#else
e336be
+#define ENA_PAGE_SIZE PAGE_SIZE
e336be
+#endif
e336be
+
e336be
 #define ENA_MIN_MSIX_VEC		2
e336be
 
e336be
 #define ENA_REG_BAR			0
e336be
@@ -362,15 +373,4 @@ void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf);
e336be
 
e336be
 int ena_get_sset_count(struct net_device *netdev, int sset);
e336be
 
e336be
-/* The ENA buffer length fields is 16 bit long. So when PAGE_SIZE == 64kB the
e336be
- * driver passas 0.
e336be
- * Since the max packet size the ENA handles is ~9kB limit the buffer length to
e336be
- * 16kB.
e336be
- */
e336be
-#if PAGE_SIZE > SZ_16K
e336be
-#define ENA_PAGE_SIZE SZ_16K
e336be
-#else
e336be
-#define ENA_PAGE_SIZE PAGE_SIZE
e336be
-#endif
e336be
-
e336be
 #endif /* !(ENA_H) */
e336be
-- 
e336be
2.19.1
e336be
e336be
From 7198e3afd93cabf55a3700cb015f59be831ecdcc Mon Sep 17 00:00:00 2001
e336be
From: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Date: Thu, 11 Oct 2018 11:26:23 +0300
e336be
Subject: [PATCH 09/16] net: ena: limit refill Rx threshold to 256 to avoid
e336be
 latency issues
e336be
e336be
Currently Rx refill is done when the number of required descriptors is
e336be
above 1/8 queue size. With a default of 1024 entries per queue the
e336be
threshold is 128 descriptors.
e336be
There is intention to increase the queue size to 8196 entries.
e336be
In this case threshold of 1024 descriptors is too large and can hurt
e336be
latency.
e336be
Add another limitation to Rx threshold to be at most 256 descriptors.
e336be
e336be
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Signed-off-by: David S. Miller <davem@davemloft.net>
e336be
---
e336be
 drivers/net/ethernet/amazon/ena/ena_netdev.c | 4 +++-
e336be
 drivers/net/ethernet/amazon/ena/ena_netdev.h | 5 +++--
e336be
 2 files changed, 6 insertions(+), 3 deletions(-)
e336be
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
index e345220b4d9a..c4c33b174e17 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
@@ -1122,7 +1122,9 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
e336be
 	rx_ring->next_to_clean = next_to_clean;
e336be
 
e336be
 	refill_required = ena_com_free_desc(rx_ring->ena_com_io_sq);
e336be
-	refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER;
e336be
+	refill_threshold =
e336be
+		min_t(int, rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER,
e336be
+		      ENA_RX_REFILL_THRESH_PACKET);
e336be
 
e336be
 	/* Optimization, try to batch new rx buffers */
e336be
 	if (refill_required > refill_threshold) {
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.h b/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
index a16baf0124d5..0cf35ae77884 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
@@ -106,10 +106,11 @@
e336be
  */
e336be
 #define ENA_TX_POLL_BUDGET_DIVIDER	4
e336be
 
e336be
-/* Refill Rx queue when number of available descriptors is below
e336be
- * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER
e336be
+/* Refill Rx queue when number of required descriptors is above
e336be
+ * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET
e336be
  */
e336be
 #define ENA_RX_REFILL_THRESH_DIVIDER	8
e336be
+#define ENA_RX_REFILL_THRESH_PACKET	256
e336be
 
e336be
 /* Number of queues to check for missing queues per timer service */
e336be
 #define ENA_MONITORED_TX_QUEUES	4
e336be
-- 
e336be
2.19.1
e336be
e336be
From 9fa751367f9fec718f4bb014e136fa5aecfb836c Mon Sep 17 00:00:00 2001
e336be
From: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Date: Thu, 11 Oct 2018 11:26:24 +0300
e336be
Subject: [PATCH 10/16] net: ena: change rx copybreak default to reduce kernel
e336be
 memory pressure
e336be
e336be
Improves socket memory utilization when receiving packets larger
e336be
than 128 bytes (the previous rx copybreak) and smaller than 256 bytes.
e336be
e336be
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Signed-off-by: David S. Miller <davem@davemloft.net>
e336be
---
e336be
 drivers/net/ethernet/amazon/ena/ena_netdev.h | 2 +-
e336be
 1 file changed, 1 insertion(+), 1 deletion(-)
e336be
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.h b/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
index 0cf35ae77884..d241dfc542ca 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
@@ -81,7 +81,7 @@
e336be
 #define ENA_DEFAULT_RING_SIZE	(1024)
e336be
 
e336be
 #define ENA_TX_WAKEUP_THRESH		(MAX_SKB_FRAGS + 2)
e336be
-#define ENA_DEFAULT_RX_COPYBREAK	(128 - NET_IP_ALIGN)
e336be
+#define ENA_DEFAULT_RX_COPYBREAK	(256 - NET_IP_ALIGN)
e336be
 
e336be
 /* limit the buffer size to 600 bytes to handle MTU changes from very
e336be
  * small to very large, in which case the number of buffers per packet
e336be
-- 
e336be
2.19.1
e336be
e336be
From 3bd1427b1dc5fff10b94528a7b0d7898b67073ce Mon Sep 17 00:00:00 2001
e336be
From: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Date: Thu, 11 Oct 2018 11:26:25 +0300
e336be
Subject: [PATCH 11/16] net: ena: remove redundant parameter in
e336be
 ena_com_admin_init()
e336be
e336be
Remove redundant spinlock acquire parameter from ena_com_admin_init()
e336be
e336be
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Signed-off-by: David S. Miller <davem@davemloft.net>
e336be
---
e336be
 drivers/net/ethernet/amazon/ena/ena_com.c    | 6 ++----
e336be
 drivers/net/ethernet/amazon/ena/ena_com.h    | 5 +----
e336be
 drivers/net/ethernet/amazon/ena/ena_netdev.c | 2 +-
e336be
 3 files changed, 4 insertions(+), 9 deletions(-)
e336be
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_com.c b/drivers/net/ethernet/amazon/ena/ena_com.c
e336be
index 5c468b28723b..420cede41ca4 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_com.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_com.c
e336be
@@ -1701,8 +1701,7 @@ void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
e336be
 }
e336be
 
e336be
 int ena_com_admin_init(struct ena_com_dev *ena_dev,
e336be
-		       struct ena_aenq_handlers *aenq_handlers,
e336be
-		       bool init_spinlock)
e336be
+		       struct ena_aenq_handlers *aenq_handlers)
e336be
 {
e336be
 	struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
e336be
 	u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
e336be
@@ -1728,8 +1727,7 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev,
e336be
 
e336be
 	atomic_set(&admin_queue->outstanding_cmds, 0);
e336be
 
e336be
-	if (init_spinlock)
e336be
-		spin_lock_init(&admin_queue->q_lock);
e336be
+	spin_lock_init(&admin_queue->q_lock);
e336be
 
e336be
 	ret = ena_com_init_comp_ctxt(admin_queue);
e336be
 	if (ret)
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_com.h b/drivers/net/ethernet/amazon/ena/ena_com.h
e336be
index 25af8d025919..ae8b4857fce3 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_com.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_com.h
e336be
@@ -436,8 +436,6 @@ void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev);
e336be
 /* ena_com_admin_init - Init the admin and the async queues
e336be
  * @ena_dev: ENA communication layer struct
e336be
  * @aenq_handlers: Those handlers to be called upon event.
e336be
- * @init_spinlock: Indicate if this method should init the admin spinlock or
e336be
- * the spinlock was init before (for example, in a case of FLR).
e336be
  *
e336be
  * Initialize the admin submission and completion queues.
e336be
  * Initialize the asynchronous events notification queues.
e336be
@@ -445,8 +443,7 @@ void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev);
e336be
  * @return - 0 on success, negative value on failure.
e336be
  */
e336be
 int ena_com_admin_init(struct ena_com_dev *ena_dev,
e336be
-		       struct ena_aenq_handlers *aenq_handlers,
e336be
-		       bool init_spinlock);
e336be
+		       struct ena_aenq_handlers *aenq_handlers);
e336be
 
e336be
 /* ena_com_admin_destroy - Destroy the admin and the async events queues.
e336be
  * @ena_dev: ENA communication layer struct
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
index c4c33b174e17..284a0a612131 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
@@ -2508,7 +2508,7 @@ static int ena_device_init(struct ena_com_dev *ena_dev, struct pci_dev *pdev,
e336be
 	}
e336be
 
e336be
 	/* ENA admin level init */
e336be
-	rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
e336be
+	rc = ena_com_admin_init(ena_dev, &aenq_handlers);
e336be
 	if (rc) {
e336be
 		dev_err(dev,
e336be
 			"Can not initialize ena admin queue with device\n");
e336be
-- 
e336be
2.19.1
e336be
e336be
From f9f5dc0c8ab71ed9b98761eea2995b46983131bf Mon Sep 17 00:00:00 2001
e336be
From: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Date: Thu, 11 Oct 2018 11:26:26 +0300
e336be
Subject: [PATCH 12/16] net: ena: update driver version to 2.0.1
e336be
e336be
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Signed-off-by: David S. Miller <davem@davemloft.net>
e336be
---
e336be
 drivers/net/ethernet/amazon/ena/ena_netdev.h | 6 +++---
e336be
 1 file changed, 3 insertions(+), 3 deletions(-)
e336be
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.h b/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
index d241dfc542ca..521873642339 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.h
e336be
@@ -43,9 +43,9 @@
e336be
 #include "ena_com.h"
e336be
 #include "ena_eth_com.h"
e336be
 
e336be
-#define DRV_MODULE_VER_MAJOR	1
e336be
-#define DRV_MODULE_VER_MINOR	5
e336be
-#define DRV_MODULE_VER_SUBMINOR 0
e336be
+#define DRV_MODULE_VER_MAJOR	2
e336be
+#define DRV_MODULE_VER_MINOR	0
e336be
+#define DRV_MODULE_VER_SUBMINOR 1
e336be
 
e336be
 #define DRV_MODULE_NAME		"ena"
e336be
 #ifndef DRV_MODULE_VERSION
e336be
-- 
e336be
2.19.1
e336be
e336be
From 24f2b7764070e2e4cd8a2b056854f1928918887e Mon Sep 17 00:00:00 2001
e336be
From: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Date: Thu, 11 Oct 2018 11:26:27 +0300
e336be
Subject: [PATCH 13/16] net: ena: fix indentations in ena_defs for better
e336be
 readability
e336be
e336be
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Signed-off-by: David S. Miller <davem@davemloft.net>
e336be
---
e336be
 .../net/ethernet/amazon/ena/ena_admin_defs.h  | 334 +++++++-----------
e336be
 .../net/ethernet/amazon/ena/ena_eth_io_defs.h | 223 ++++++------
e336be
 .../net/ethernet/amazon/ena/ena_regs_defs.h   | 206 +++++------
e336be
 3 files changed, 338 insertions(+), 425 deletions(-)
e336be
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_admin_defs.h b/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
e336be
index b439ec1b3edb..9f80b73f90b1 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_admin_defs.h
e336be
@@ -32,119 +32,81 @@
e336be
 #ifndef _ENA_ADMIN_H_
e336be
 #define _ENA_ADMIN_H_
e336be
 
e336be
-enum ena_admin_aq_opcode {
e336be
-	ENA_ADMIN_CREATE_SQ	= 1,
e336be
-
e336be
-	ENA_ADMIN_DESTROY_SQ	= 2,
e336be
-
e336be
-	ENA_ADMIN_CREATE_CQ	= 3,
e336be
-
e336be
-	ENA_ADMIN_DESTROY_CQ	= 4,
e336be
-
e336be
-	ENA_ADMIN_GET_FEATURE	= 8,
e336be
 
e336be
-	ENA_ADMIN_SET_FEATURE	= 9,
e336be
-
e336be
-	ENA_ADMIN_GET_STATS	= 11,
e336be
+enum ena_admin_aq_opcode {
e336be
+	ENA_ADMIN_CREATE_SQ                         = 1,
e336be
+	ENA_ADMIN_DESTROY_SQ                        = 2,
e336be
+	ENA_ADMIN_CREATE_CQ                         = 3,
e336be
+	ENA_ADMIN_DESTROY_CQ                        = 4,
e336be
+	ENA_ADMIN_GET_FEATURE                       = 8,
e336be
+	ENA_ADMIN_SET_FEATURE                       = 9,
e336be
+	ENA_ADMIN_GET_STATS                         = 11,
e336be
 };
e336be
 
e336be
 enum ena_admin_aq_completion_status {
e336be
-	ENA_ADMIN_SUCCESS			= 0,
e336be
-
e336be
-	ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE	= 1,
e336be
-
e336be
-	ENA_ADMIN_BAD_OPCODE			= 2,
e336be
-
e336be
-	ENA_ADMIN_UNSUPPORTED_OPCODE		= 3,
e336be
-
e336be
-	ENA_ADMIN_MALFORMED_REQUEST		= 4,
e336be
-
e336be
+	ENA_ADMIN_SUCCESS                           = 0,
e336be
+	ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE       = 1,
e336be
+	ENA_ADMIN_BAD_OPCODE                        = 2,
e336be
+	ENA_ADMIN_UNSUPPORTED_OPCODE                = 3,
e336be
+	ENA_ADMIN_MALFORMED_REQUEST                 = 4,
e336be
 	/* Additional status is provided in ACQ entry extended_status */
e336be
-	ENA_ADMIN_ILLEGAL_PARAMETER		= 5,
e336be
-
e336be
-	ENA_ADMIN_UNKNOWN_ERROR			= 6,
e336be
-
e336be
-	ENA_ADMIN_RESOURCE_BUSY                 = 7,
e336be
+	ENA_ADMIN_ILLEGAL_PARAMETER                 = 5,
e336be
+	ENA_ADMIN_UNKNOWN_ERROR                     = 6,
e336be
+	ENA_ADMIN_RESOURCE_BUSY                     = 7,
e336be
 };
e336be
 
e336be
 enum ena_admin_aq_feature_id {
e336be
-	ENA_ADMIN_DEVICE_ATTRIBUTES		= 1,
e336be
-
e336be
-	ENA_ADMIN_MAX_QUEUES_NUM		= 2,
e336be
-
e336be
-	ENA_ADMIN_HW_HINTS			= 3,
e336be
-
e336be
-	ENA_ADMIN_LLQ                           = 4,
e336be
-
e336be
-	ENA_ADMIN_RSS_HASH_FUNCTION		= 10,
e336be
-
e336be
-	ENA_ADMIN_STATELESS_OFFLOAD_CONFIG	= 11,
e336be
-
e336be
-	ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG	= 12,
e336be
-
e336be
-	ENA_ADMIN_MTU				= 14,
e336be
-
e336be
-	ENA_ADMIN_RSS_HASH_INPUT		= 18,
e336be
-
e336be
-	ENA_ADMIN_INTERRUPT_MODERATION		= 20,
e336be
-
e336be
-	ENA_ADMIN_AENQ_CONFIG			= 26,
e336be
-
e336be
-	ENA_ADMIN_LINK_CONFIG			= 27,
e336be
-
e336be
-	ENA_ADMIN_HOST_ATTR_CONFIG		= 28,
e336be
-
e336be
-	ENA_ADMIN_FEATURES_OPCODE_NUM		= 32,
e336be
+	ENA_ADMIN_DEVICE_ATTRIBUTES                 = 1,
e336be
+	ENA_ADMIN_MAX_QUEUES_NUM                    = 2,
e336be
+	ENA_ADMIN_HW_HINTS                          = 3,
e336be
+	ENA_ADMIN_LLQ                               = 4,
e336be
+	ENA_ADMIN_RSS_HASH_FUNCTION                 = 10,
e336be
+	ENA_ADMIN_STATELESS_OFFLOAD_CONFIG          = 11,
e336be
+	ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG      = 12,
e336be
+	ENA_ADMIN_MTU                               = 14,
e336be
+	ENA_ADMIN_RSS_HASH_INPUT                    = 18,
e336be
+	ENA_ADMIN_INTERRUPT_MODERATION              = 20,
e336be
+	ENA_ADMIN_AENQ_CONFIG                       = 26,
e336be
+	ENA_ADMIN_LINK_CONFIG                       = 27,
e336be
+	ENA_ADMIN_HOST_ATTR_CONFIG                  = 28,
e336be
+	ENA_ADMIN_FEATURES_OPCODE_NUM               = 32,
e336be
 };
e336be
 
e336be
 enum ena_admin_placement_policy_type {
e336be
 	/* descriptors and headers are in host memory */
e336be
-	ENA_ADMIN_PLACEMENT_POLICY_HOST	= 1,
e336be
-
e336be
+	ENA_ADMIN_PLACEMENT_POLICY_HOST             = 1,
e336be
 	/* descriptors and headers are in device memory (a.k.a Low Latency
e336be
 	 * Queue)
e336be
 	 */
e336be
-	ENA_ADMIN_PLACEMENT_POLICY_DEV	= 3,
e336be
+	ENA_ADMIN_PLACEMENT_POLICY_DEV              = 3,
e336be
 };
e336be
 
e336be
 enum ena_admin_link_types {
e336be
-	ENA_ADMIN_LINK_SPEED_1G		= 0x1,
e336be
-
e336be
-	ENA_ADMIN_LINK_SPEED_2_HALF_G	= 0x2,
e336be
-
e336be
-	ENA_ADMIN_LINK_SPEED_5G		= 0x4,
e336be
-
e336be
-	ENA_ADMIN_LINK_SPEED_10G	= 0x8,
e336be
-
e336be
-	ENA_ADMIN_LINK_SPEED_25G	= 0x10,
e336be
-
e336be
-	ENA_ADMIN_LINK_SPEED_40G	= 0x20,
e336be
-
e336be
-	ENA_ADMIN_LINK_SPEED_50G	= 0x40,
e336be
-
e336be
-	ENA_ADMIN_LINK_SPEED_100G	= 0x80,
e336be
-
e336be
-	ENA_ADMIN_LINK_SPEED_200G	= 0x100,
e336be
-
e336be
-	ENA_ADMIN_LINK_SPEED_400G	= 0x200,
e336be
+	ENA_ADMIN_LINK_SPEED_1G                     = 0x1,
e336be
+	ENA_ADMIN_LINK_SPEED_2_HALF_G               = 0x2,
e336be
+	ENA_ADMIN_LINK_SPEED_5G                     = 0x4,
e336be
+	ENA_ADMIN_LINK_SPEED_10G                    = 0x8,
e336be
+	ENA_ADMIN_LINK_SPEED_25G                    = 0x10,
e336be
+	ENA_ADMIN_LINK_SPEED_40G                    = 0x20,
e336be
+	ENA_ADMIN_LINK_SPEED_50G                    = 0x40,
e336be
+	ENA_ADMIN_LINK_SPEED_100G                   = 0x80,
e336be
+	ENA_ADMIN_LINK_SPEED_200G                   = 0x100,
e336be
+	ENA_ADMIN_LINK_SPEED_400G                   = 0x200,
e336be
 };
e336be
 
e336be
 enum ena_admin_completion_policy_type {
e336be
 	/* completion queue entry for each sq descriptor */
e336be
-	ENA_ADMIN_COMPLETION_POLICY_DESC		= 0,
e336be
-
e336be
+	ENA_ADMIN_COMPLETION_POLICY_DESC            = 0,
e336be
 	/* completion queue entry upon request in sq descriptor */
e336be
-	ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND	= 1,
e336be
-
e336be
+	ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND  = 1,
e336be
 	/* current queue head pointer is updated in OS memory upon sq
e336be
 	 * descriptor request
e336be
 	 */
e336be
-	ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND	= 2,
e336be
-
e336be
+	ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND  = 2,
e336be
 	/* current queue head pointer is updated in OS memory for each sq
e336be
 	 * descriptor
e336be
 	 */
e336be
-	ENA_ADMIN_COMPLETION_POLICY_HEAD		= 3,
e336be
+	ENA_ADMIN_COMPLETION_POLICY_HEAD            = 3,
e336be
 };
e336be
 
e336be
 /* basic stats return ena_admin_basic_stats while extanded stats return a
e336be
@@ -152,15 +114,13 @@ enum ena_admin_completion_policy_type {
e336be
  * device id
e336be
  */
e336be
 enum ena_admin_get_stats_type {
e336be
-	ENA_ADMIN_GET_STATS_TYPE_BASIC		= 0,
e336be
-
e336be
-	ENA_ADMIN_GET_STATS_TYPE_EXTENDED	= 1,
e336be
+	ENA_ADMIN_GET_STATS_TYPE_BASIC              = 0,
e336be
+	ENA_ADMIN_GET_STATS_TYPE_EXTENDED           = 1,
e336be
 };
e336be
 
e336be
 enum ena_admin_get_stats_scope {
e336be
-	ENA_ADMIN_SPECIFIC_QUEUE	= 0,
e336be
-
e336be
-	ENA_ADMIN_ETH_TRAFFIC		= 1,
e336be
+	ENA_ADMIN_SPECIFIC_QUEUE                    = 0,
e336be
+	ENA_ADMIN_ETH_TRAFFIC                       = 1,
e336be
 };
e336be
 
e336be
 struct ena_admin_aq_common_desc {
e336be
@@ -231,7 +191,9 @@ struct ena_admin_acq_common_desc {
e336be
 
e336be
 	u16 extended_status;
e336be
 
e336be
-	/* serves as a hint what AQ entries can be revoked */
e336be
+	/* indicates to the driver which AQ entry has been consumed by the
e336be
+	 *    device and could be reused
e336be
+	 */
e336be
 	u16 sq_head_indx;
e336be
 };
e336be
 
e336be
@@ -300,9 +262,8 @@ struct ena_admin_aq_create_sq_cmd {
e336be
 };
e336be
 
e336be
 enum ena_admin_sq_direction {
e336be
-	ENA_ADMIN_SQ_DIRECTION_TX	= 1,
e336be
-
e336be
-	ENA_ADMIN_SQ_DIRECTION_RX	= 2,
e336be
+	ENA_ADMIN_SQ_DIRECTION_TX                   = 1,
e336be
+	ENA_ADMIN_SQ_DIRECTION_RX                   = 2,
e336be
 };
e336be
 
e336be
 struct ena_admin_acq_create_sq_resp_desc {
e336be
@@ -664,9 +625,8 @@ struct ena_admin_feature_offload_desc {
e336be
 };
e336be
 
e336be
 enum ena_admin_hash_functions {
e336be
-	ENA_ADMIN_TOEPLITZ	= 1,
e336be
-
e336be
-	ENA_ADMIN_CRC32		= 2,
e336be
+	ENA_ADMIN_TOEPLITZ                          = 1,
e336be
+	ENA_ADMIN_CRC32                             = 2,
e336be
 };
e336be
 
e336be
 struct ena_admin_feature_rss_flow_hash_control {
e336be
@@ -692,50 +652,35 @@ struct ena_admin_feature_rss_flow_hash_function {
e336be
 
e336be
 /* RSS flow hash protocols */
e336be
 enum ena_admin_flow_hash_proto {
e336be
-	ENA_ADMIN_RSS_TCP4	= 0,
e336be
-
e336be
-	ENA_ADMIN_RSS_UDP4	= 1,
e336be
-
e336be
-	ENA_ADMIN_RSS_TCP6	= 2,
e336be
-
e336be
-	ENA_ADMIN_RSS_UDP6	= 3,
e336be
-
e336be
-	ENA_ADMIN_RSS_IP4	= 4,
e336be
-
e336be
-	ENA_ADMIN_RSS_IP6	= 5,
e336be
-
e336be
-	ENA_ADMIN_RSS_IP4_FRAG	= 6,
e336be
-
e336be
-	ENA_ADMIN_RSS_NOT_IP	= 7,
e336be
-
e336be
+	ENA_ADMIN_RSS_TCP4                          = 0,
e336be
+	ENA_ADMIN_RSS_UDP4                          = 1,
e336be
+	ENA_ADMIN_RSS_TCP6                          = 2,
e336be
+	ENA_ADMIN_RSS_UDP6                          = 3,
e336be
+	ENA_ADMIN_RSS_IP4                           = 4,
e336be
+	ENA_ADMIN_RSS_IP6                           = 5,
e336be
+	ENA_ADMIN_RSS_IP4_FRAG                      = 6,
e336be
+	ENA_ADMIN_RSS_NOT_IP                        = 7,
e336be
 	/* TCPv6 with extension header */
e336be
-	ENA_ADMIN_RSS_TCP6_EX	= 8,
e336be
-
e336be
+	ENA_ADMIN_RSS_TCP6_EX                       = 8,
e336be
 	/* IPv6 with extension header */
e336be
-	ENA_ADMIN_RSS_IP6_EX	= 9,
e336be
-
e336be
-	ENA_ADMIN_RSS_PROTO_NUM	= 16,
e336be
+	ENA_ADMIN_RSS_IP6_EX                        = 9,
e336be
+	ENA_ADMIN_RSS_PROTO_NUM                     = 16,
e336be
 };
e336be
 
e336be
 /* RSS flow hash fields */
e336be
 enum ena_admin_flow_hash_fields {
e336be
 	/* Ethernet Dest Addr */
e336be
-	ENA_ADMIN_RSS_L2_DA	= BIT(0),
e336be
-
e336be
+	ENA_ADMIN_RSS_L2_DA                         = BIT(0),
e336be
 	/* Ethernet Src Addr */
e336be
-	ENA_ADMIN_RSS_L2_SA	= BIT(1),
e336be
-
e336be
+	ENA_ADMIN_RSS_L2_SA                         = BIT(1),
e336be
 	/* ipv4/6 Dest Addr */
e336be
-	ENA_ADMIN_RSS_L3_DA	= BIT(2),
e336be
-
e336be
+	ENA_ADMIN_RSS_L3_DA                         = BIT(2),
e336be
 	/* ipv4/6 Src Addr */
e336be
-	ENA_ADMIN_RSS_L3_SA	= BIT(3),
e336be
-
e336be
+	ENA_ADMIN_RSS_L3_SA                         = BIT(3),
e336be
 	/* tcp/udp Dest Port */
e336be
-	ENA_ADMIN_RSS_L4_DP	= BIT(4),
e336be
-
e336be
+	ENA_ADMIN_RSS_L4_DP                         = BIT(4),
e336be
 	/* tcp/udp Src Port */
e336be
-	ENA_ADMIN_RSS_L4_SP	= BIT(5),
e336be
+	ENA_ADMIN_RSS_L4_SP                         = BIT(5),
e336be
 };
e336be
 
e336be
 struct ena_admin_proto_input {
e336be
@@ -774,19 +719,13 @@ struct ena_admin_feature_rss_flow_hash_input {
e336be
 };
e336be
 
e336be
 enum ena_admin_os_type {
e336be
-	ENA_ADMIN_OS_LINUX	= 1,
e336be
-
e336be
-	ENA_ADMIN_OS_WIN	= 2,
e336be
-
e336be
-	ENA_ADMIN_OS_DPDK	= 3,
e336be
-
e336be
-	ENA_ADMIN_OS_FREEBSD	= 4,
e336be
-
e336be
-	ENA_ADMIN_OS_IPXE	= 5,
e336be
-
e336be
-	ENA_ADMIN_OS_ESXI       = 6,
e336be
-
e336be
-	ENA_ADMIN_OS_GROUPS_NUM = 6,
e336be
+	ENA_ADMIN_OS_LINUX                          = 1,
e336be
+	ENA_ADMIN_OS_WIN                            = 2,
e336be
+	ENA_ADMIN_OS_DPDK                           = 3,
e336be
+	ENA_ADMIN_OS_FREEBSD                        = 4,
e336be
+	ENA_ADMIN_OS_IPXE                           = 5,
e336be
+	ENA_ADMIN_OS_ESXI			    = 6,
e336be
+	ENA_ADMIN_OS_GROUPS_NUM			    = 6,
e336be
 };
e336be
 
e336be
 struct ena_admin_host_info {
e336be
@@ -981,25 +920,18 @@ struct ena_admin_aenq_common_desc {
e336be
 
e336be
 /* asynchronous event notification groups */
e336be
 enum ena_admin_aenq_group {
e336be
-	ENA_ADMIN_LINK_CHANGE		= 0,
e336be
-
e336be
-	ENA_ADMIN_FATAL_ERROR		= 1,
e336be
-
e336be
-	ENA_ADMIN_WARNING		= 2,
e336be
-
e336be
-	ENA_ADMIN_NOTIFICATION		= 3,
e336be
-
e336be
-	ENA_ADMIN_KEEP_ALIVE		= 4,
e336be
-
e336be
-	ENA_ADMIN_AENQ_GROUPS_NUM	= 5,
e336be
+	ENA_ADMIN_LINK_CHANGE                       = 0,
e336be
+	ENA_ADMIN_FATAL_ERROR                       = 1,
e336be
+	ENA_ADMIN_WARNING                           = 2,
e336be
+	ENA_ADMIN_NOTIFICATION                      = 3,
e336be
+	ENA_ADMIN_KEEP_ALIVE                        = 4,
e336be
+	ENA_ADMIN_AENQ_GROUPS_NUM                   = 5,
e336be
 };
e336be
 
e336be
 enum ena_admin_aenq_notification_syndrom {
e336be
-	ENA_ADMIN_SUSPEND	= 0,
e336be
-
e336be
-	ENA_ADMIN_RESUME	= 1,
e336be
-
e336be
-	ENA_ADMIN_UPDATE_HINTS	= 2,
e336be
+	ENA_ADMIN_SUSPEND                           = 0,
e336be
+	ENA_ADMIN_RESUME                            = 1,
e336be
+	ENA_ADMIN_UPDATE_HINTS                      = 2,
e336be
 };
e336be
 
e336be
 struct ena_admin_aenq_entry {
e336be
@@ -1034,27 +966,27 @@ struct ena_admin_ena_mmio_req_read_less_resp {
e336be
 };
e336be
 
e336be
 /* aq_common_desc */
e336be
-#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
e336be
-#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
e336be
-#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
e336be
-#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
e336be
-#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
e336be
-#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
e336be
+#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK            GENMASK(11, 0)
e336be
+#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK                 BIT(0)
e336be
+#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT            1
e336be
+#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK             BIT(1)
e336be
+#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT   2
e336be
+#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK    BIT(2)
e336be
 
e336be
 /* sq */
e336be
-#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
e336be
-#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
e336be
+#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT                     5
e336be
+#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK                      GENMASK(7, 5)
e336be
 
e336be
 /* acq_common_desc */
e336be
-#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
e336be
-#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
e336be
+#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK           GENMASK(11, 0)
e336be
+#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK                BIT(0)
e336be
 
e336be
 /* aq_create_sq_cmd */
e336be
-#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
e336be
-#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
e336be
-#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
e336be
-#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
e336be
-#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
e336be
+#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT       5
e336be
+#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK        GENMASK(7, 5)
e336be
+#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK    GENMASK(3, 0)
e336be
+#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT  4
e336be
+#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK   GENMASK(6, 4)
e336be
 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
e336be
 
e336be
 /* aq_create_cq_cmd */
e336be
@@ -1063,12 +995,12 @@ struct ena_admin_ena_mmio_req_read_less_resp {
e336be
 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
e336be
 
e336be
 /* get_set_feature_common_desc */
e336be
-#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
e336be
+#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK   GENMASK(1, 0)
e336be
 
e336be
 /* get_feature_link_desc */
e336be
-#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
e336be
-#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
e336be
-#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
e336be
+#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK        BIT(0)
e336be
+#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT        1
e336be
+#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK         BIT(1)
e336be
 
e336be
 /* feature_offload_desc */
e336be
 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
e336be
@@ -1080,19 +1012,19 @@ struct ena_admin_ena_mmio_req_read_less_resp {
e336be
 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
e336be
 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
e336be
 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
e336be
-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
e336be
-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
e336be
-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
e336be
-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
e336be
-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
e336be
-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
e336be
+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT       5
e336be
+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK        BIT(5)
e336be
+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT       6
e336be
+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK        BIT(6)
e336be
+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT        7
e336be
+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK         BIT(7)
e336be
 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
e336be
 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
e336be
 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
e336be
 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
e336be
 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
e336be
-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
e336be
-#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
e336be
+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT        3
e336be
+#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK         BIT(3)
e336be
 
e336be
 /* feature_rss_flow_hash_function */
e336be
 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
e336be
@@ -1100,32 +1032,32 @@ struct ena_admin_ena_mmio_req_read_less_resp {
e336be
 
e336be
 /* feature_rss_flow_hash_input */
e336be
 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
e336be
-#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
e336be
+#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK  BIT(1)
e336be
 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
e336be
-#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
e336be
+#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK  BIT(2)
e336be
 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
e336be
 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
e336be
 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
e336be
 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
e336be
 
e336be
 /* host_info */
e336be
-#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
e336be
-#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
e336be
-#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
e336be
-#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
e336be
-#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
e336be
-#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
e336be
-#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
e336be
-#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
e336be
-#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
e336be
-#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
e336be
-#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
e336be
-#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
e336be
+#define ENA_ADMIN_HOST_INFO_MAJOR_MASK                      GENMASK(7, 0)
e336be
+#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT                     8
e336be
+#define ENA_ADMIN_HOST_INFO_MINOR_MASK                      GENMASK(15, 8)
e336be
+#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT                 16
e336be
+#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK                  GENMASK(23, 16)
e336be
+#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT               24
e336be
+#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK                GENMASK(31, 24)
e336be
+#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK                   GENMASK(2, 0)
e336be
+#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT                    3
e336be
+#define ENA_ADMIN_HOST_INFO_DEVICE_MASK                     GENMASK(7, 3)
e336be
+#define ENA_ADMIN_HOST_INFO_BUS_SHIFT                       8
e336be
+#define ENA_ADMIN_HOST_INFO_BUS_MASK                        GENMASK(15, 8)
e336be
 
e336be
 /* aenq_common_desc */
e336be
-#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
e336be
+#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK               BIT(0)
e336be
 
e336be
 /* aenq_link_change_desc */
e336be
-#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
e336be
+#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK    BIT(0)
e336be
 
e336be
 #endif /*_ENA_ADMIN_H_ */
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h b/drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h
e336be
index 4c5ccaa13c42..00e0f056a741 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h
e336be
@@ -33,25 +33,18 @@
e336be
 #define _ENA_ETH_IO_H_
e336be
 
e336be
 enum ena_eth_io_l3_proto_index {
e336be
-	ENA_ETH_IO_L3_PROTO_UNKNOWN	= 0,
e336be
-
e336be
-	ENA_ETH_IO_L3_PROTO_IPV4	= 8,
e336be
-
e336be
-	ENA_ETH_IO_L3_PROTO_IPV6	= 11,
e336be
-
e336be
-	ENA_ETH_IO_L3_PROTO_FCOE	= 21,
e336be
-
e336be
-	ENA_ETH_IO_L3_PROTO_ROCE	= 22,
e336be
+	ENA_ETH_IO_L3_PROTO_UNKNOWN                 = 0,
e336be
+	ENA_ETH_IO_L3_PROTO_IPV4                    = 8,
e336be
+	ENA_ETH_IO_L3_PROTO_IPV6                    = 11,
e336be
+	ENA_ETH_IO_L3_PROTO_FCOE                    = 21,
e336be
+	ENA_ETH_IO_L3_PROTO_ROCE                    = 22,
e336be
 };
e336be
 
e336be
 enum ena_eth_io_l4_proto_index {
e336be
-	ENA_ETH_IO_L4_PROTO_UNKNOWN		= 0,
e336be
-
e336be
-	ENA_ETH_IO_L4_PROTO_TCP			= 12,
e336be
-
e336be
-	ENA_ETH_IO_L4_PROTO_UDP			= 13,
e336be
-
e336be
-	ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE	= 23,
e336be
+	ENA_ETH_IO_L4_PROTO_UNKNOWN                 = 0,
e336be
+	ENA_ETH_IO_L4_PROTO_TCP                     = 12,
e336be
+	ENA_ETH_IO_L4_PROTO_UDP                     = 13,
e336be
+	ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE          = 23,
e336be
 };
e336be
 
e336be
 struct ena_eth_io_tx_desc {
e336be
@@ -307,116 +300,116 @@ struct ena_eth_io_numa_node_cfg_reg {
e336be
 };
e336be
 
e336be
 /* tx_desc */
e336be
-#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
e336be
-#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
e336be
-#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
e336be
-#define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
e336be
-#define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
e336be
-#define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
e336be
-#define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
e336be
-#define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
e336be
-#define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
e336be
-#define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
e336be
-#define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
e336be
-#define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
e336be
-#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
e336be
-#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
e336be
-#define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
e336be
-#define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
e336be
-#define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
e336be
-#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
e336be
-#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
e336be
-#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
e336be
-#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
e336be
-#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
e336be
-#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
e336be
-#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
e336be
-#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
e336be
-#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
e336be
-#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
e336be
-#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
e336be
-#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
e336be
-#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
e336be
-#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
e336be
-#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
e336be
-#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
e336be
+#define ENA_ETH_IO_TX_DESC_LENGTH_MASK                      GENMASK(15, 0)
e336be
+#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT                  16
e336be
+#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK                   GENMASK(21, 16)
e336be
+#define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT                  23
e336be
+#define ENA_ETH_IO_TX_DESC_META_DESC_MASK                   BIT(23)
e336be
+#define ENA_ETH_IO_TX_DESC_PHASE_SHIFT                      24
e336be
+#define ENA_ETH_IO_TX_DESC_PHASE_MASK                       BIT(24)
e336be
+#define ENA_ETH_IO_TX_DESC_FIRST_SHIFT                      26
e336be
+#define ENA_ETH_IO_TX_DESC_FIRST_MASK                       BIT(26)
e336be
+#define ENA_ETH_IO_TX_DESC_LAST_SHIFT                       27
e336be
+#define ENA_ETH_IO_TX_DESC_LAST_MASK                        BIT(27)
e336be
+#define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT                   28
e336be
+#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK                    BIT(28)
e336be
+#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK                GENMASK(3, 0)
e336be
+#define ENA_ETH_IO_TX_DESC_DF_SHIFT                         4
e336be
+#define ENA_ETH_IO_TX_DESC_DF_MASK                          BIT(4)
e336be
+#define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT                     7
e336be
+#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK                      BIT(7)
e336be
+#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT               8
e336be
+#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK                GENMASK(12, 8)
e336be
+#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT                 13
e336be
+#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK                  BIT(13)
e336be
+#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT                 14
e336be
+#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK                  BIT(14)
e336be
+#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT           15
e336be
+#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK            BIT(15)
e336be
+#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT            17
e336be
+#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK             BIT(17)
e336be
+#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT                  22
e336be
+#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK                   GENMASK(31, 22)
e336be
+#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK                     GENMASK(15, 0)
e336be
+#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT              24
e336be
+#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK               GENMASK(31, 24)
e336be
 
e336be
 /* tx_meta_desc */
e336be
-#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
e336be
-#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
e336be
-#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
e336be
-#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
e336be
-#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
e336be
-#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
e336be
-#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
e336be
-#define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
e336be
-#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
e336be
-#define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
e336be
-#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
e336be
-#define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
e336be
-#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
e336be
-#define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
e336be
-#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
e336be
-#define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
e336be
-#define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
e336be
-#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
e336be
-#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
e336be
-#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
e336be
-#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
e336be
-#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
e336be
-#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
e336be
-#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
e336be
-#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
e336be
-#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
e336be
-#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
e336be
+#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK              GENMASK(9, 0)
e336be
+#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT             14
e336be
+#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK              BIT(14)
e336be
+#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT                16
e336be
+#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK                 GENMASK(19, 16)
e336be
+#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT         20
e336be
+#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK          BIT(20)
e336be
+#define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT            21
e336be
+#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK             BIT(21)
e336be
+#define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT             23
e336be
+#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK              BIT(23)
e336be
+#define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT                 24
e336be
+#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK                  BIT(24)
e336be
+#define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT                 26
e336be
+#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK                  BIT(26)
e336be
+#define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT                  27
e336be
+#define ENA_ETH_IO_TX_META_DESC_LAST_MASK                   BIT(27)
e336be
+#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT              28
e336be
+#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK               BIT(28)
e336be
+#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK              GENMASK(5, 0)
e336be
+#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK             GENMASK(7, 0)
e336be
+#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT            8
e336be
+#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK             GENMASK(15, 8)
e336be
+#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT   16
e336be
+#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK    GENMASK(21, 16)
e336be
+#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT                22
e336be
+#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK                 GENMASK(31, 22)
e336be
 
e336be
 /* tx_cdesc */
e336be
-#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
e336be
+#define ENA_ETH_IO_TX_CDESC_PHASE_MASK                      BIT(0)
e336be
 
e336be
 /* rx_desc */
e336be
-#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
e336be
-#define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
e336be
-#define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
e336be
-#define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
e336be
-#define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
e336be
-#define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
e336be
-#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
e336be
+#define ENA_ETH_IO_RX_DESC_PHASE_MASK                       BIT(0)
e336be
+#define ENA_ETH_IO_RX_DESC_FIRST_SHIFT                      2
e336be
+#define ENA_ETH_IO_RX_DESC_FIRST_MASK                       BIT(2)
e336be
+#define ENA_ETH_IO_RX_DESC_LAST_SHIFT                       3
e336be
+#define ENA_ETH_IO_RX_DESC_LAST_MASK                        BIT(3)
e336be
+#define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT                   4
e336be
+#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK                    BIT(4)
e336be
 
e336be
 /* rx_cdesc_base */
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16)
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
e336be
-#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK          GENMASK(4, 0)
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT         5
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK          GENMASK(6, 5)
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT         8
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK          GENMASK(12, 8)
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT          13
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK           BIT(13)
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT          14
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK           BIT(14)
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT            15
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK             BIT(15)
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT      16
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK       BIT(16)
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT                24
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK                 BIT(24)
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT             25
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK              BIT(25)
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT                26
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK                 BIT(26)
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT                 27
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK                  BIT(27)
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT               30
e336be
+#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK                BIT(30)
e336be
 
e336be
 /* intr_reg */
e336be
-#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
e336be
-#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
e336be
-#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
e336be
-#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
e336be
-#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
e336be
+#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK              GENMASK(14, 0)
e336be
+#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT             15
e336be
+#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK              GENMASK(29, 15)
e336be
+#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT               30
e336be
+#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK                BIT(30)
e336be
 
e336be
 /* numa_node_cfg_reg */
e336be
-#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
e336be
-#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
e336be
-#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
e336be
+#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK              GENMASK(7, 0)
e336be
+#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT          31
e336be
+#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK           BIT(31)
e336be
 
e336be
 #endif /*_ENA_ETH_IO_H_ */
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_regs_defs.h b/drivers/net/ethernet/amazon/ena/ena_regs_defs.h
e336be
index 48ca97fbe7bc..04fcafcc059c 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_regs_defs.h
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_regs_defs.h
e336be
@@ -33,137 +33,125 @@
e336be
 #define _ENA_REGS_H_
e336be
 
e336be
 enum ena_regs_reset_reason_types {
e336be
-	ENA_REGS_RESET_NORMAL			= 0,
e336be
-
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-	ENA_REGS_RESET_KEEP_ALIVE_TO		= 1,
e336be
-
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-	ENA_REGS_RESET_ADMIN_TO			= 2,
e336be
-
e336be
-	ENA_REGS_RESET_MISS_TX_CMPL		= 3,
e336be
-
e336be
-	ENA_REGS_RESET_INV_RX_REQ_ID		= 4,
e336be
-
e336be
-	ENA_REGS_RESET_INV_TX_REQ_ID		= 5,
e336be
-
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-	ENA_REGS_RESET_TOO_MANY_RX_DESCS	= 6,
e336be
-
e336be
-	ENA_REGS_RESET_INIT_ERR			= 7,
e336be
-
e336be
-	ENA_REGS_RESET_DRIVER_INVALID_STATE	= 8,
e336be
-
e336be
-	ENA_REGS_RESET_OS_TRIGGER		= 9,
e336be
-
e336be
-	ENA_REGS_RESET_OS_NETDEV_WD		= 10,
e336be
-
e336be
-	ENA_REGS_RESET_SHUTDOWN			= 11,
e336be
-
e336be
-	ENA_REGS_RESET_USER_TRIGGER		= 12,
e336be
-
e336be
-	ENA_REGS_RESET_GENERIC			= 13,
e336be
-
e336be
-	ENA_REGS_RESET_MISS_INTERRUPT		= 14,
e336be
+	ENA_REGS_RESET_NORMAL                       = 0,
e336be
+	ENA_REGS_RESET_KEEP_ALIVE_TO                = 1,
e336be
+	ENA_REGS_RESET_ADMIN_TO                     = 2,
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+	ENA_REGS_RESET_MISS_TX_CMPL                 = 3,
e336be
+	ENA_REGS_RESET_INV_RX_REQ_ID                = 4,
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+	ENA_REGS_RESET_INV_TX_REQ_ID                = 5,
e336be
+	ENA_REGS_RESET_TOO_MANY_RX_DESCS            = 6,
e336be
+	ENA_REGS_RESET_INIT_ERR                     = 7,
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+	ENA_REGS_RESET_DRIVER_INVALID_STATE         = 8,
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+	ENA_REGS_RESET_OS_TRIGGER                   = 9,
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+	ENA_REGS_RESET_OS_NETDEV_WD                 = 10,
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+	ENA_REGS_RESET_SHUTDOWN                     = 11,
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+	ENA_REGS_RESET_USER_TRIGGER                 = 12,
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+	ENA_REGS_RESET_GENERIC                      = 13,
e336be
+	ENA_REGS_RESET_MISS_INTERRUPT               = 14,
e336be
 };
e336be
 
e336be
 /* ena_registers offsets */
e336be
-#define ENA_REGS_VERSION_OFF		0x0
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-#define ENA_REGS_CONTROLLER_VERSION_OFF		0x4
e336be
-#define ENA_REGS_CAPS_OFF		0x8
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-#define ENA_REGS_CAPS_EXT_OFF		0xc
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-#define ENA_REGS_AQ_BASE_LO_OFF		0x10
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-#define ENA_REGS_AQ_BASE_HI_OFF		0x14
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-#define ENA_REGS_AQ_CAPS_OFF		0x18
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-#define ENA_REGS_ACQ_BASE_LO_OFF		0x20
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-#define ENA_REGS_ACQ_BASE_HI_OFF		0x24
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-#define ENA_REGS_ACQ_CAPS_OFF		0x28
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-#define ENA_REGS_AQ_DB_OFF		0x2c
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-#define ENA_REGS_ACQ_TAIL_OFF		0x30
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-#define ENA_REGS_AENQ_CAPS_OFF		0x34
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-#define ENA_REGS_AENQ_BASE_LO_OFF		0x38
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-#define ENA_REGS_AENQ_BASE_HI_OFF		0x3c
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-#define ENA_REGS_AENQ_HEAD_DB_OFF		0x40
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-#define ENA_REGS_AENQ_TAIL_OFF		0x44
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-#define ENA_REGS_INTR_MASK_OFF		0x4c
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-#define ENA_REGS_DEV_CTL_OFF		0x54
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-#define ENA_REGS_DEV_STS_OFF		0x58
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-#define ENA_REGS_MMIO_REG_READ_OFF		0x5c
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-#define ENA_REGS_MMIO_RESP_LO_OFF		0x60
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-#define ENA_REGS_MMIO_RESP_HI_OFF		0x64
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-#define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF		0x68
e336be
+
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+/* 0 base */
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+#define ENA_REGS_VERSION_OFF                                0x0
e336be
+#define ENA_REGS_CONTROLLER_VERSION_OFF                     0x4
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+#define ENA_REGS_CAPS_OFF                                   0x8
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+#define ENA_REGS_CAPS_EXT_OFF                               0xc
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+#define ENA_REGS_AQ_BASE_LO_OFF                             0x10
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+#define ENA_REGS_AQ_BASE_HI_OFF                             0x14
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+#define ENA_REGS_AQ_CAPS_OFF                                0x18
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+#define ENA_REGS_ACQ_BASE_LO_OFF                            0x20
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+#define ENA_REGS_ACQ_BASE_HI_OFF                            0x24
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+#define ENA_REGS_ACQ_CAPS_OFF                               0x28
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+#define ENA_REGS_AQ_DB_OFF                                  0x2c
e336be
+#define ENA_REGS_ACQ_TAIL_OFF                               0x30
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+#define ENA_REGS_AENQ_CAPS_OFF                              0x34
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+#define ENA_REGS_AENQ_BASE_LO_OFF                           0x38
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+#define ENA_REGS_AENQ_BASE_HI_OFF                           0x3c
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+#define ENA_REGS_AENQ_HEAD_DB_OFF                           0x40
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+#define ENA_REGS_AENQ_TAIL_OFF                              0x44
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+#define ENA_REGS_INTR_MASK_OFF                              0x4c
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+#define ENA_REGS_DEV_CTL_OFF                                0x54
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+#define ENA_REGS_DEV_STS_OFF                                0x58
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+#define ENA_REGS_MMIO_REG_READ_OFF                          0x5c
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+#define ENA_REGS_MMIO_RESP_LO_OFF                           0x60
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+#define ENA_REGS_MMIO_RESP_HI_OFF                           0x64
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+#define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF                   0x68
e336be
 
e336be
 /* version register */
e336be
-#define ENA_REGS_VERSION_MINOR_VERSION_MASK		0xff
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-#define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT		8
e336be
-#define ENA_REGS_VERSION_MAJOR_VERSION_MASK		0xff00
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+#define ENA_REGS_VERSION_MINOR_VERSION_MASK                 0xff
e336be
+#define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT                8
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+#define ENA_REGS_VERSION_MAJOR_VERSION_MASK                 0xff00
e336be
 
e336be
 /* controller_version register */
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-#define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK		0xff
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-#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT		8
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-#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK		0xff00
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-#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT		16
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-#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK		0xff0000
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-#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT		24
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-#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK		0xff000000
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+#define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK   0xff
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+#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT     8
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+#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK      0xff00
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+#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT     16
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+#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK      0xff0000
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+#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT           24
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+#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK            0xff000000
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e336be
 /* caps register */
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-#define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK		0x1
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-#define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT		1
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-#define ENA_REGS_CAPS_RESET_TIMEOUT_MASK		0x3e
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-#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT		8
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-#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK		0xff00
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-#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT		16
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-#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK		0xf0000
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+#define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK        0x1
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+#define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT                   1
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+#define ENA_REGS_CAPS_RESET_TIMEOUT_MASK                    0x3e
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+#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT                  8
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+#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK                   0xff00
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+#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT                    16
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+#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK                     0xf0000
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e336be
 /* aq_caps register */
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-#define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK		0xffff
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-#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT		16
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-#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK		0xffff0000
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+#define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK                      0xffff
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+#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT                16
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+#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK                 0xffff0000
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e336be
 /* acq_caps register */
e336be
-#define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK		0xffff
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-#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT		16
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-#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK		0xffff0000
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+#define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK                    0xffff
e336be
+#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT              16
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+#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK               0xffff0000
e336be
 
e336be
 /* aenq_caps register */
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-#define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK		0xffff
e336be
-#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT		16
e336be
-#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK		0xffff0000
e336be
+#define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK                  0xffff
e336be
+#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT            16
e336be
+#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK             0xffff0000
e336be
 
e336be
 /* dev_ctl register */
e336be
-#define ENA_REGS_DEV_CTL_DEV_RESET_MASK		0x1
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-#define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT		1
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-#define ENA_REGS_DEV_CTL_AQ_RESTART_MASK		0x2
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-#define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT		2
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-#define ENA_REGS_DEV_CTL_QUIESCENT_MASK		0x4
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-#define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT		3
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-#define ENA_REGS_DEV_CTL_IO_RESUME_MASK		0x8
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-#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT		28
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-#define ENA_REGS_DEV_CTL_RESET_REASON_MASK		0xf0000000
e336be
+#define ENA_REGS_DEV_CTL_DEV_RESET_MASK                     0x1
e336be
+#define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT                   1
e336be
+#define ENA_REGS_DEV_CTL_AQ_RESTART_MASK                    0x2
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+#define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT                    2
e336be
+#define ENA_REGS_DEV_CTL_QUIESCENT_MASK                     0x4
e336be
+#define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT                    3
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+#define ENA_REGS_DEV_CTL_IO_RESUME_MASK                     0x8
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+#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT                 28
e336be
+#define ENA_REGS_DEV_CTL_RESET_REASON_MASK                  0xf0000000
e336be
 
e336be
 /* dev_sts register */
e336be
-#define ENA_REGS_DEV_STS_READY_MASK		0x1
e336be
-#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT		1
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-#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK		0x2
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-#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT		2
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-#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK		0x4
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-#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT		3
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-#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK		0x8
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-#define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT		4
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-#define ENA_REGS_DEV_STS_RESET_FINISHED_MASK		0x10
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-#define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT		5
e336be
-#define ENA_REGS_DEV_STS_FATAL_ERROR_MASK		0x20
e336be
-#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT		6
e336be
-#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK		0x40
e336be
-#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT		7
e336be
-#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK		0x80
e336be
+#define ENA_REGS_DEV_STS_READY_MASK                         0x1
e336be
+#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT       1
e336be
+#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK        0x2
e336be
+#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT          2
e336be
+#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK           0x4
e336be
+#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT            3
e336be
+#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK             0x8
e336be
+#define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT               4
e336be
+#define ENA_REGS_DEV_STS_RESET_FINISHED_MASK                0x10
e336be
+#define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT                  5
e336be
+#define ENA_REGS_DEV_STS_FATAL_ERROR_MASK                   0x20
e336be
+#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT  6
e336be
+#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK   0x40
e336be
+#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT     7
e336be
+#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK      0x80
e336be
 
e336be
 /* mmio_reg_read register */
e336be
-#define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK		0xffff
e336be
-#define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT		16
e336be
-#define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK		0xffff0000
e336be
+#define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK                  0xffff
e336be
+#define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT                16
e336be
+#define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK                 0xffff0000
e336be
 
e336be
 /* rss_ind_entry_update register */
e336be
-#define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK		0xffff
e336be
-#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT		16
e336be
-#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK		0xffff0000
e336be
+#define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK            0xffff
e336be
+#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT          16
e336be
+#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK           0xffff0000
e336be
 
e336be
 #endif /*_ENA_REGS_H_ */
e336be
-- 
e336be
2.19.1
e336be
e336be
From 6c2e2e6731d872a227226140780c8ecd9712bf4e Mon Sep 17 00:00:00 2001
e336be
From: Netanel Belgazal <netanel@amazon.com>
e336be
Date: Wed, 17 Oct 2018 10:04:21 +0000
e336be
Subject: [PATCH 14/16] net: ena: Fix Kconfig dependency on X86
e336be
e336be
The Kconfig limitation of X86 is to too wide.
e336be
The ENA driver only requires a little endian dependency.
e336be
e336be
Change the dependency to be on little endian CPU.
e336be
e336be
Signed-off-by: Netanel Belgazal <netanel@amazon.com>
e336be
Signed-off-by: David S. Miller <davem@davemloft.net>
e336be
---
e336be
 drivers/net/ethernet/amazon/Kconfig | 2 +-
e336be
 1 file changed, 1 insertion(+), 1 deletion(-)
e336be
e336be
diff --git a/drivers/net/ethernet/amazon/Kconfig b/drivers/net/ethernet/amazon/Kconfig
e336be
index 99b30353541a..9e87d7b8360f 100644
e336be
--- a/drivers/net/ethernet/amazon/Kconfig
e336be
+++ b/drivers/net/ethernet/amazon/Kconfig
e336be
@@ -17,7 +17,7 @@ if NET_VENDOR_AMAZON
e336be
 
e336be
 config ENA_ETHERNET
e336be
 	tristate "Elastic Network Adapter (ENA) support"
e336be
-	depends on (PCI_MSI && X86)
e336be
+	depends on PCI_MSI && !CPU_BIG_ENDIAN
e336be
 	---help---
e336be
 	  This driver supports Elastic Network Adapter (ENA)"
e336be
 
e336be
-- 
e336be
2.19.1
e336be
e336be
From 628f8c52965bb8734f76bbeb2b24b20bc48d2180 Mon Sep 17 00:00:00 2001
e336be
From: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Date: Wed, 17 Oct 2018 15:33:23 +0300
e336be
Subject: [PATCH 15/16] net: ena: enable Low Latency Queues
e336be
e336be
Use the new API to enable usage of LLQ.
e336be
e336be
Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Signed-off-by: David S. Miller <davem@davemloft.net>
e336be
---
e336be
 drivers/net/ethernet/amazon/ena/ena_netdev.c | 18 ++++--------------
e336be
 1 file changed, 4 insertions(+), 14 deletions(-)
e336be
e336be
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
index 284a0a612131..18956e7604a3 100644
e336be
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
e336be
@@ -3022,20 +3022,10 @@ static int ena_calc_io_queue_num(struct pci_dev *pdev,
e336be
 	int io_sq_num, io_queue_num;
e336be
 
e336be
 	/* In case of LLQ use the llq number in the get feature cmd */
e336be
-	if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
e336be
-		io_sq_num = get_feat_ctx->max_queues.max_legacy_llq_num;
e336be
-
e336be
-		if (io_sq_num == 0) {
e336be
-			dev_err(&pdev->dev,
e336be
-				"Trying to use LLQ but llq_num is 0. Fall back into regular queues\n");
e336be
-
e336be
-			ena_dev->tx_mem_queue_type =
e336be
-				ENA_ADMIN_PLACEMENT_POLICY_HOST;
e336be
-			io_sq_num = get_feat_ctx->max_queues.max_sq_num;
e336be
-		}
e336be
-	} else {
e336be
+	if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
e336be
+		io_sq_num = get_feat_ctx->llq.max_llq_num;
e336be
+	else
e336be
 		io_sq_num = get_feat_ctx->max_queues.max_sq_num;
e336be
-	}
e336be
 
e336be
 	io_queue_num = min_t(int, num_online_cpus(), ENA_MAX_NUM_IO_QUEUES);
e336be
 	io_queue_num = min_t(int, io_queue_num, io_sq_num);
e336be
@@ -3238,7 +3228,7 @@ static int ena_calc_queue_size(struct pci_dev *pdev,
e336be
 
e336be
 	if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
e336be
 		queue_size = min_t(u32, queue_size,
e336be
-				   get_feat_ctx->max_queues.max_legacy_llq_depth);
e336be
+				   get_feat_ctx->llq.max_llq_depth);
e336be
 
e336be
 	queue_size = rounddown_pow_of_two(queue_size);
e336be
 
e336be
-- 
e336be
2.19.1
e336be
e336be
From 3d31772392bcd5c9fc8a493df6c9f58ca6930e50 Mon Sep 17 00:00:00 2001
e336be
From: Arthur Kiyanovski <akiyano@amazon.com>
e336be
Date: Sun, 21 Oct 2018 18:07:14 +0300
e336be
Subject: [PATCH 16/16] net: ena: fix compilation error in xtensa architecture
e336be
e336be
linux/prefetch.h is never explicitly included in ena_com, although
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functions from it, such as prefetchw(), are used throughout ena_com.
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This is an inclusion bug, and we fix it here by explicitly including
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linux/prefetch.h. The bug was exposed when the driver was compiled
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for the xtensa architecture.
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Fixes: 689b2bdaaa14 ("net: ena: add functions for handling Low Latency Queues in ena_com")
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Fixes: 8c590f977638 ("ena: Fix Kconfig dependency on X86")
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Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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 drivers/net/ethernet/amazon/ena/ena_com.h | 1 +
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 1 file changed, 1 insertion(+)
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diff --git a/drivers/net/ethernet/amazon/ena/ena_com.h b/drivers/net/ethernet/amazon/ena/ena_com.h
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index ae8b4857fce3..078d6f2b4f39 100644
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--- a/drivers/net/ethernet/amazon/ena/ena_com.h
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+++ b/drivers/net/ethernet/amazon/ena/ena_com.h
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@@ -38,6 +38,7 @@
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 #include <linux/dma-mapping.h>
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 #include <linux/gfp.h>
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 #include <linux/io.h>
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+#include <linux/prefetch.h>
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 #include <linux/sched.h>
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 #include <linux/sizes.h>
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 #include <linux/spinlock.h>
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-- 
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2.19.1
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