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From patchwork Wed Apr 6 07:54:05 2016
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: usb: phy: tegra: Add 38.4MHz clock table entry
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From: Hunter Laux <hunterlaux@gmail.com>
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X-Patchwork-Id: 606877
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Message-Id: <1459929245-23449-1-git-send-email-hunterlaux@gmail.com>
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To: Stephen Warren <swarren@wwwdotorg.org>,
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Thierry Reding <thierry.reding@gmail.com>,
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Alexandre Courbot <gnurou@gmail.com>, linux-tegra@vger.kernel.org
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Cc: Hunter Laux <hunterlaux@gmail.com>
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Date: Wed, 6 Apr 2016 00:54:05 -0700
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The Tegra210 uses a 38.4MHz OSC. This clock table entry is required to
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use the ehci phy on the Jetson TX1.
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The xtal_freq_count is actually a 12 bit value, so it should be a u16
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instead of u8.
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Signed-off-by: Hunter Laux <hunterlaux@gmail.com>
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---
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drivers/usb/phy/phy-tegra-usb.c | 10 +++++++++-
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1 file changed, 9 insertions(+), 1 deletion(-)
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diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c
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index 5fe4a57..f0431f0 100644
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--- a/drivers/usb/phy/phy-tegra-usb.c
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+++ b/drivers/usb/phy/phy-tegra-usb.c
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@@ -164,7 +164,7 @@ struct tegra_xtal_freq {
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u8 enable_delay;
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u8 stable_count;
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u8 active_delay;
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- u8 xtal_freq_count;
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+ u16 xtal_freq_count;
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u16 debounce;
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};
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@@ -201,6 +201,14 @@ static const struct tegra_xtal_freq tegra_freq_table[] = {
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.xtal_freq_count = 0xFE,
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.debounce = 0xFDE8,
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},
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+ {
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+ .freq = 38400000,
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+ .enable_delay = 0x00,
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+ .stable_count = 0x00,
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+ .active_delay = 0x18,
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+ .xtal_freq_count = 0x177,
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+ .debounce = 0xBB80,
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+ },
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};
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static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
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