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From: Uenal Mutlu <um@mutluit.com>
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To: Jens Axboe <axboe@kernel.dk>, Maxime Ripard <maxime.ripard@bootlin.com>,
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Subject: [PATCH v3] drivers: ata: ahci_sunxi: Increased SATA/AHCI DMA TX/RX
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 FIFOs
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Date: Mon, 13 May 2019 16:24:10 +0200
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Cc: Mark Rutland <mark.rutland@arm.com>, Uenal Mutlu <um@mutluit.com>,
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 Oliver Schinagl <oliver@schinagl.nl>,
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 Pablo Greco <pgreco@centosproject.org>, FUKAUMI Naoki <naobsd@gmail.com>,
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 Hans de Goede <hdegoede@redhat.com>, linux-sunxi@googlegroups.com,
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 Jagan Teki <jagan@amarulasolutions.com>, linux-amarula@amarulasolutions.com,
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Increasing the SATA/AHCI DMA TX/RX FIFOs (P0DMACR.TXTS and .RXTS, ie.
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TX_TRANSACTION_SIZE and RX_TRANSACTION_SIZE) from default 0x0 each
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to 0x3 each, gives a write performance boost of 120 MiB/s to 132 MiB/s
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from lame 36 MiB/s to 45 MiB/s previously.
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Read performance is above 200 MiB/s.
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[tested on SSD using dd bs=4K/8K/12K/16K/20K/24K/32K: peak-perf at 12K]
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Tested on the SBCs Banana Pi R1 (aka Lamobo R1) and Banana Pi M1 which
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are based on the Allwinner A20 32bit-SoC (ARMv7-a / arm-linux-gnueabihf).
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These devices are RaspberryPi-like small devices.
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This problem of slow SATA write-speed with these small devices lasts
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for about 7 years now (beginning with the A10 SoC). Many commentators
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throughout the years wrongly assumed the slow write speed was a
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hardware limitation. This patch finally solves the problem, which
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in fact was just a hard-to-find software problem due to lack of
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SATA/AHCI documentation by the SoC-maker Allwinner Technology.
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Lists of the affected sunxi and other boards and SoCs with SATA using
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the ahci_sunxi driver:
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  $ grep -i -e "^&ahci" arch/arm/boot/dts/sun*dts
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  and http://linux-sunxi.org/SATA#Devices_with_SATA_ports
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  See also http://linux-sunxi.org/Category:Devices_with_SATA_port
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Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Reviewed-by: Hans de Goede <hdegoede@redhat.com>
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Signed-off-by: Uenal Mutlu <um@mutluit.com>
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---
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v3:
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  * Removed RFC from Subject line, and also the explicit call for RFC
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    in the text, thereby submitting the patch for official merging.
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v2:
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  * Commented the patch in-place in ahci_sunxi.c
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  * With bs=12K and no conv=... passed to dd, the write performance
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    rises further to 132 MiB/s
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  * Changed MB/s to MiB/s
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  * Posted the story behind the patch:
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    http://lkml.iu.edu/hypermail/linux/kernel/1905.1/03506.html
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  * Posted a dd test script to find optimal bs, and some results:
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    https://bit.ly/2YoOzEM
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v1:
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  * States bs=4K for dd and a write performance of 120 MiB/s
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---
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 drivers/ata/ahci_sunxi.c | 47 +++++++++++++++++++++++++++++++++++++++++++++--
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 1 file changed, 45 insertions(+), 2 deletions(-)
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diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
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index 911710643305..018186a39a69 100644
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--- a/drivers/ata/ahci_sunxi.c
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+++ b/drivers/ata/ahci_sunxi.c
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@@ -157,8 +157,51 @@ static void ahci_sunxi_start_engine(struct ata_port *ap)
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 	void __iomem *port_mmio = ahci_port_base(ap);
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 	struct ahci_host_priv *hpriv = ap->host->private_data;
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-	/* Setup DMA before DMA start */
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-	sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
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+	/* Setup DMA before DMA start
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+	 *
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+	 * NOTE: A similar SoC with SATA/AHCI by Texas Instruments documents
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+	 *   this Vendor Specific Port (P0DMACR, aka PxDMACR) in its
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+	 *   User's Guide document (TMS320C674x/OMAP-L1x Processor
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+	 *   Serial ATA (SATA) Controller, Literature Number: SPRUGJ8C,
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+	 *   March 2011, Chapter 4.33 Port DMA Control Register (P0DMACR),
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+	 *   p.68, https://www.ti.com/lit/ug/sprugj8c/sprugj8c.pdf)
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+	 *   as equivalent to the following struct:
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+	 *
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+	 *   struct AHCI_P0DMACR_t
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+	 *   {
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+	 *     unsigned TXTS     : 4;
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+	 *     unsigned RXTS     : 4;
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+	 *     unsigned TXABL    : 4;
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+	 *     unsigned RXABL    : 4;
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+	 *     unsigned Reserved : 16;
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+	 *   };
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+	 *
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+	 *   TXTS: Transmit Transaction Size (TX_TRANSACTION_SIZE).
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+	 *     This field defines the DMA transaction size in DWORDs for
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+	 *     transmit (system bus read, device write) operation. [...]
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+	 *
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+	 *   RXTS: Receive Transaction Size (RX_TRANSACTION_SIZE).
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+	 *     This field defines the Port DMA transaction size in DWORDs
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+	 *     for receive (system bus write, device read) operation. [...]
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+	 *
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+	 *   TXABL: Transmit Burst Limit.
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+	 *     This field allows software to limit the VBUSP master read
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+	 *     burst size. [...]
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+	 *
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+	 *   RXABL: Receive Burst Limit.
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+	 *     Allows software to limit the VBUSP master write burst
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+	 *     size. [...]
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+	 *
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+	 *   Reserved: Reserved.
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+	 *
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+	 *
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+	 * NOTE: According to the above document, the following alternative
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+	 *   to the code below could perhaps be a better option
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+	 *   (or preparation) for possible further improvements later:
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+	 *     sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff,
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+	 *		0x00000033);
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+	 */
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+	sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff, 0x00004433);
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 	/* Start DMA */
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 	sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);