dcavalca / rpms / qemu

Forked from rpms/qemu a year ago
Clone

Blame 0097-tcg-i386-fix-build-with-march-i686.patch

5544c1
From 5d3868bb343df0c13240521e36d0cc942c7a2d04 Mon Sep 17 00:00:00 2001
5544c1
From: Aurelien Jarno <aurelien@aurel32.net>
5544c1
Date: Wed, 26 Sep 2012 00:30:12 +0200
5544c1
Subject: [PATCH] tcg/i386: fix build with -march < i686
5544c1
5544c1
The movcond_i32 op has to be protected with TCG_TARGET_HAS_movcond_i32
5544c1
to fix the build with -march < i686.
5544c1
5544c1
Thanks to Richard Henderson for the hint.
5544c1
5544c1
Reported-by: Alex Barcelo <abarcelo@ac.upc.edu>
5544c1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
5544c1
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
5544c1
---
5544c1
 tcg/i386/tcg-target.c | 2 ++
5544c1
 1 file changed, 2 insertions(+)
5544c1
5544c1
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
5544c1
index 85c6b81..616ef23 100644
5544c1
--- a/tcg/i386/tcg-target.c
5544c1
+++ b/tcg/i386/tcg-target.c
5544c1
@@ -1907,7 +1907,9 @@ static const TCGTargetOpDef x86_op_defs[] = {
5544c1
     { INDEX_op_setcond_i32, { "q", "r", "ri" } },
5544c1
 
5544c1
     { INDEX_op_deposit_i32, { "Q", "0", "Q" } },
5544c1
+#if TCG_TARGET_HAS_movcond_i32
5544c1
     { INDEX_op_movcond_i32, { "r", "r", "ri", "r", "0" } },
5544c1
+#endif
5544c1
 
5544c1
 #if TCG_TARGET_REG_BITS == 32
5544c1
     { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
5544c1
-- 
5544c1
1.7.12.1
5544c1