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From 12e60f780a097837840ab1e7bb7d54b8c15112e8 Mon Sep 17 00:00:00 2001
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From: Richard Henderson <rth@twiddle.net>
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Date: Sun, 25 Mar 2012 21:36:28 +0200
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Subject: [PATCH] tcg-sparc: Mask shift immediates to avoid illegal insns.
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The xtensa-test image generates a sra_i32 with count 0x40.
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Whether this is accident of tcg constant propagation or
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originating directly from the instruction stream is immaterial.
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Signed-off-by: Richard Henderson <rth@twiddle.net>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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tcg/sparc/tcg-target.c | 18 ++++++++++++------
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1 file changed, 12 insertions(+), 6 deletions(-)
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diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
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index e625aa3..be5c170 100644
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--- a/tcg/sparc/tcg-target.c
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+++ b/tcg/sparc/tcg-target.c
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@@ -1154,13 +1154,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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goto gen_arith;
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case INDEX_op_shl_i32:
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c = SHIFT_SLL;
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- goto gen_arith;
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+ do_shift32:
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+ /* Limit immediate shift count lest we create an illegal insn. */
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+ tcg_out_arithc(s, args[0], args[1], args[2] & 31, const_args[2], c);
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+ break;
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case INDEX_op_shr_i32:
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c = SHIFT_SRL;
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- goto gen_arith;
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+ goto do_shift32;
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case INDEX_op_sar_i32:
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c = SHIFT_SRA;
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- goto gen_arith;
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+ goto do_shift32;
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case INDEX_op_mul_i32:
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c = ARITH_UMUL;
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goto gen_arith;
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@@ -1281,13 +1284,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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break;
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case INDEX_op_shl_i64:
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c = SHIFT_SLLX;
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- goto gen_arith;
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+ do_shift64:
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+ /* Limit immediate shift count lest we create an illegal insn. */
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+ tcg_out_arithc(s, args[0], args[1], args[2] & 63, const_args[2], c);
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+ break;
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case INDEX_op_shr_i64:
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c = SHIFT_SRLX;
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- goto gen_arith;
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+ goto do_shift64;
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case INDEX_op_sar_i64:
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c = SHIFT_SRAX;
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- goto gen_arith;
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+ goto do_shift64;
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case INDEX_op_mul_i64:
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c = ARITH_MULX;
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goto gen_arith;
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--
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1.7.12.1
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