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Blame 0033-target-arm-final-conversion-to-AREG0-free-mode.patch

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From 28b8f097f9fb107882aa51bd25ba87619beb033e Mon Sep 17 00:00:00 2001
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From: Blue Swirl <blauwirbel@gmail.com>
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Date: Tue, 4 Sep 2012 20:25:59 +0000
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Subject: [PATCH] target-arm: final conversion to AREG0 free mode
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Convert code load functions and switch to AREG0 free mode.
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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 configure                |  2 +-
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 target-arm/Makefile.objs |  2 --
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 target-arm/cpu.h         | 10 ++++++----
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 target-arm/helper.c      |  9 +++++----
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 target-arm/op_helper.c   |  8 +-------
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 target-arm/translate.c   |  6 +++---
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 6 files changed, 16 insertions(+), 21 deletions(-)
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diff --git a/configure b/configure
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index a8827ba..e8806f0 100755
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--- a/configure
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+++ b/configure
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@@ -3839,7 +3839,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
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 case "$target_arch2" in
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-  alpha | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
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+  alpha | arm* | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
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     echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
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   ;;
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 esac
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diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
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index f447c4f..b6f1a9e 100644
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--- a/target-arm/Makefile.objs
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+++ b/target-arm/Makefile.objs
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@@ -2,5 +2,3 @@ obj-y += arm-semi.o
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 obj-$(CONFIG_SOFTMMU) += machine.o
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 obj-y += translate.o op_helper.o helper.o cpu.o
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 obj-y += neon_helper.o iwmmxt_helper.o
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-
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-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
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diff --git a/target-arm/cpu.h b/target-arm/cpu.h
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index d7f93d9..7fac94f 100644
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--- a/target-arm/cpu.h
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+++ b/target-arm/cpu.h
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@@ -734,9 +734,10 @@ static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
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 }
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 /* Load an instruction and return it in the standard little-endian order */
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-static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
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+static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
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+                                    bool do_swap)
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 {
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-    uint32_t insn = ldl_code(addr);
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+    uint32_t insn = cpu_ldl_code(env, addr);
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     if (do_swap) {
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         return bswap32(insn);
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     }
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@@ -744,9 +745,10 @@ static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
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 }
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 /* Ditto, for a halfword (Thumb) instruction */
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-static inline uint16_t arm_lduw_code(uint32_t addr, bool do_swap)
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+static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr,
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+                                     bool do_swap)
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 {
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-    uint16_t insn = lduw_code(addr);
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+    uint16_t insn = cpu_lduw_code(env, addr);
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     if (do_swap) {
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         return bswap16(insn);
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     }
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diff --git a/target-arm/helper.c b/target-arm/helper.c
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index e27df96..58340bd 100644
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--- a/target-arm/helper.c
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+++ b/target-arm/helper.c
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@@ -1756,7 +1756,7 @@ static void do_interrupt_v7m(CPUARMState *env)
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     case EXCP_BKPT:
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         if (semihosting_enabled) {
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             int nr;
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-            nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
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+            nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
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             if (nr == 0xab) {
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                 env->regs[15] += 2;
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                 env->regs[0] = do_arm_semihosting(env);
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@@ -1828,9 +1828,10 @@ void do_interrupt(CPUARMState *env)
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         if (semihosting_enabled) {
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             /* Check for semihosting interrupt.  */
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             if (env->thumb) {
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-                mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 0xff;
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+                mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
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+                    & 0xff;
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             } else {
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-                mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
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+                mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
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                     & 0xffffff;
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             }
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             /* Only intercept calls from privileged modes, to provide some
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@@ -1851,7 +1852,7 @@ void do_interrupt(CPUARMState *env)
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     case EXCP_BKPT:
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         /* See if this is a semihosting syscall.  */
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         if (env->thumb && semihosting_enabled) {
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-            mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
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+            mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
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             if (mask == 0xab
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                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
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                 env->regs[15] += 2;
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diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
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index 5b868bf..f13fc3a 100644
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--- a/target-arm/op_helper.c
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+++ b/target-arm/op_helper.c
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@@ -17,7 +17,6 @@
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  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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  */
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 #include "cpu.h"
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-#include "dyngen-exec.h"
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 #include "helper.h"
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 #define SIGNBIT (uint32_t)0x80000000
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@@ -72,16 +71,12 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
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 /* try to fill the TLB and return an exception if error. If retaddr is
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    NULL, it means that the function was called in C code (i.e. not
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    from generated code or from helper.c) */
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-/* XXX: fix it to restore all registers */
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-void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
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+void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
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               uintptr_t retaddr)
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 {
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     TranslationBlock *tb;
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-    CPUARMState *saved_env;
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     int ret;
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-    saved_env = env;
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-    env = env1;
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     ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
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     if (unlikely(ret)) {
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         if (retaddr) {
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@@ -95,7 +90,6 @@ void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
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         }
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         raise_exception(env, env->exception_index);
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     }
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-    env = saved_env;
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 }
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 #endif
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diff --git a/target-arm/translate.c b/target-arm/translate.c
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index 9ae3b26..f4b447a 100644
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--- a/target-arm/translate.c
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+++ b/target-arm/translate.c
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@@ -6534,7 +6534,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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     TCGv addr;
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     TCGv_i64 tmp64;
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-    insn = arm_ldl_code(s->pc, s->bswap_code);
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+    insn = arm_ldl_code(env, s->pc, s->bswap_code);
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     s->pc += 4;
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     /* M variants do not implement ARM mode.  */
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@@ -7962,7 +7962,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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         /* Fall through to 32-bit decode.  */
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     }
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-    insn = arm_lduw_code(s->pc, s->bswap_code);
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+    insn = arm_lduw_code(env, s->pc, s->bswap_code);
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     s->pc += 2;
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     insn |= (uint32_t)insn_hw1 << 16;
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@@ -8992,7 +8992,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
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         }
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     }
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-    insn = arm_lduw_code(s->pc, s->bswap_code);
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+    insn = arm_lduw_code(env, s->pc, s->bswap_code);
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     s->pc += 2;
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     switch (insn >> 12) {
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-- 
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1.7.12.1
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