dcavalca / rpms / qemu

Forked from rpms/qemu a year ago
Clone

Blame 0032-target-arm-convert-remaining-helpers.patch

5544c1
From 18e713cf6b5ae2e7c48bb412c959c10322bef5e5 Mon Sep 17 00:00:00 2001
5544c1
From: Blue Swirl <blauwirbel@gmail.com>
5544c1
Date: Tue, 4 Sep 2012 20:19:15 +0000
5544c1
Subject: [PATCH] target-arm: convert remaining helpers
5544c1
5544c1
Convert remaining helpers to AREG0 free mode: add an explicit
5544c1
CPUState parameter instead of relying on AREG0.
5544c1
5544c1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
5544c1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5544c1
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
5544c1
---
5544c1
 target-arm/helper.h    |  52 +++++++++----------
5544c1
 target-arm/op_helper.c |  64 +++++++++++------------
5544c1
 target-arm/translate.c | 134 ++++++++++++++++++++++++-------------------------
5544c1
 3 files changed, 125 insertions(+), 125 deletions(-)
5544c1
5544c1
diff --git a/target-arm/helper.h b/target-arm/helper.h
5544c1
index 106aacd..afdb2b5 100644
5544c1
--- a/target-arm/helper.h
5544c1
+++ b/target-arm/helper.h
5544c1
@@ -4,12 +4,12 @@ DEF_HELPER_1(clz, i32, i32)
5544c1
 DEF_HELPER_1(sxtb16, i32, i32)
5544c1
 DEF_HELPER_1(uxtb16, i32, i32)
5544c1
 
5544c1
-DEF_HELPER_2(add_setq, i32, i32, i32)
5544c1
-DEF_HELPER_2(add_saturate, i32, i32, i32)
5544c1
-DEF_HELPER_2(sub_saturate, i32, i32, i32)
5544c1
-DEF_HELPER_2(add_usaturate, i32, i32, i32)
5544c1
-DEF_HELPER_2(sub_usaturate, i32, i32, i32)
5544c1
-DEF_HELPER_1(double_saturate, i32, s32)
5544c1
+DEF_HELPER_3(add_setq, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(add_saturate, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(sub_saturate, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
5544c1
+DEF_HELPER_2(double_saturate, i32, env, s32)
5544c1
 DEF_HELPER_2(sdiv, s32, s32, s32)
5544c1
 DEF_HELPER_2(udiv, i32, i32, i32)
5544c1
 DEF_HELPER_1(rbit, i32, i32)
5544c1
@@ -40,10 +40,10 @@ PAS_OP(uq)
5544c1
 PAS_OP(uh)
5544c1
 #undef PAS_OP
5544c1
 
5544c1
-DEF_HELPER_2(ssat, i32, i32, i32)
5544c1
-DEF_HELPER_2(usat, i32, i32, i32)
5544c1
-DEF_HELPER_2(ssat16, i32, i32, i32)
5544c1
-DEF_HELPER_2(usat16, i32, i32, i32)
5544c1
+DEF_HELPER_3(ssat, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(usat, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(ssat16, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(usat16, i32, env, i32, i32)
5544c1
 
5544c1
 DEF_HELPER_2(usad8, i32, i32, i32)
5544c1
 
5544c1
@@ -54,7 +54,7 @@ DEF_HELPER_2(exception, void, env, i32)
5544c1
 DEF_HELPER_1(wfi, void, env)
5544c1
 
5544c1
 DEF_HELPER_3(cpsr_write, void, env, i32, i32)
5544c1
-DEF_HELPER_0(cpsr_read, i32)
5544c1
+DEF_HELPER_1(cpsr_read, i32, env)
5544c1
 
5544c1
 DEF_HELPER_3(v7m_msr, void, env, i32, i32)
5544c1
 DEF_HELPER_2(v7m_mrs, i32, env, i32)
5544c1
@@ -67,7 +67,7 @@ DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
5544c1
 DEF_HELPER_2(get_r13_banked, i32, env, i32)
5544c1
 DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
5544c1
 
5544c1
-DEF_HELPER_1(get_user_reg, i32, i32)
5544c1
+DEF_HELPER_2(get_user_reg, i32, env, i32)
5544c1
 DEF_HELPER_3(set_user_reg, void, env, i32, i32)
5544c1
 
5544c1
 DEF_HELPER_1(vfp_get_fpscr, i32, env)
5544c1
@@ -140,20 +140,20 @@ DEF_HELPER_2(recpe_f32, f32, f32, env)
5544c1
 DEF_HELPER_2(rsqrte_f32, f32, f32, env)
5544c1
 DEF_HELPER_2(recpe_u32, i32, i32, env)
5544c1
 DEF_HELPER_2(rsqrte_u32, i32, i32, env)
5544c1
-DEF_HELPER_4(neon_tbl, i32, i32, i32, i32, i32)
5544c1
-
5544c1
-DEF_HELPER_2(add_cc, i32, i32, i32)
5544c1
-DEF_HELPER_2(adc_cc, i32, i32, i32)
5544c1
-DEF_HELPER_2(sub_cc, i32, i32, i32)
5544c1
-DEF_HELPER_2(sbc_cc, i32, i32, i32)
5544c1
-
5544c1
-DEF_HELPER_2(shl, i32, i32, i32)
5544c1
-DEF_HELPER_2(shr, i32, i32, i32)
5544c1
-DEF_HELPER_2(sar, i32, i32, i32)
5544c1
-DEF_HELPER_2(shl_cc, i32, i32, i32)
5544c1
-DEF_HELPER_2(shr_cc, i32, i32, i32)
5544c1
-DEF_HELPER_2(sar_cc, i32, i32, i32)
5544c1
-DEF_HELPER_2(ror_cc, i32, i32, i32)
5544c1
+DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32)
5544c1
+
5544c1
+DEF_HELPER_3(add_cc, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(adc_cc, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(sub_cc, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(sbc_cc, i32, env, i32, i32)
5544c1
+
5544c1
+DEF_HELPER_3(shl, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(shr, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(sar, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(shl_cc, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(shr_cc, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(sar_cc, i32, env, i32, i32)
5544c1
+DEF_HELPER_3(ror_cc, i32, env, i32, i32)
5544c1
 
5544c1
 /* neon_helper.c */
5544c1
 DEF_HELPER_3(neon_qadd_u8, i32, env, i32, i32)
5544c1
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
5544c1
index b1adce3..5b868bf 100644
5544c1
--- a/target-arm/op_helper.c
5544c1
+++ b/target-arm/op_helper.c
5544c1
@@ -29,7 +29,7 @@ static void raise_exception(CPUARMState *env, int tt)
5544c1
     cpu_loop_exit(env);
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
5544c1
+uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
5544c1
                           uint32_t rn, uint32_t maxindex)
5544c1
 {
5544c1
     uint32_t val;
5544c1
@@ -101,7 +101,7 @@ void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
5544c1
 
5544c1
 /* FIXME: Pass an explicit pointer to QF to CPUARMState, and move saturating
5544c1
    instructions into helper.c  */
5544c1
-uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
5544c1
+uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
5544c1
 {
5544c1
     uint32_t res = a + b;
5544c1
     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
5544c1
@@ -109,7 +109,7 @@ uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
5544c1
     return res;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b)
5544c1
+uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
5544c1
 {
5544c1
     uint32_t res = a + b;
5544c1
     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
5544c1
@@ -119,7 +119,7 @@ uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b)
5544c1
     return res;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b)
5544c1
+uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
5544c1
 {
5544c1
     uint32_t res = a - b;
5544c1
     if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
5544c1
@@ -129,7 +129,7 @@ uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b)
5544c1
     return res;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(double_saturate)(int32_t val)
5544c1
+uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
5544c1
 {
5544c1
     uint32_t res;
5544c1
     if (val >= 0x40000000) {
5544c1
@@ -144,7 +144,7 @@ uint32_t HELPER(double_saturate)(int32_t val)
5544c1
     return res;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(add_usaturate)(uint32_t a, uint32_t b)
5544c1
+uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
5544c1
 {
5544c1
     uint32_t res = a + b;
5544c1
     if (res < a) {
5544c1
@@ -154,7 +154,7 @@ uint32_t HELPER(add_usaturate)(uint32_t a, uint32_t b)
5544c1
     return res;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(sub_usaturate)(uint32_t a, uint32_t b)
5544c1
+uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
5544c1
 {
5544c1
     uint32_t res = a - b;
5544c1
     if (res > a) {
5544c1
@@ -165,7 +165,7 @@ uint32_t HELPER(sub_usaturate)(uint32_t a, uint32_t b)
5544c1
 }
5544c1
 
5544c1
 /* Signed saturation.  */
5544c1
-static inline uint32_t do_ssat(int32_t val, int shift)
5544c1
+static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
5544c1
 {
5544c1
     int32_t top;
5544c1
     uint32_t mask;
5544c1
@@ -183,7 +183,7 @@ static inline uint32_t do_ssat(int32_t val, int shift)
5544c1
 }
5544c1
 
5544c1
 /* Unsigned saturation.  */
5544c1
-static inline uint32_t do_usat(int32_t val, int shift)
5544c1
+static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
5544c1
 {
5544c1
     uint32_t max;
5544c1
 
5544c1
@@ -199,34 +199,34 @@ static inline uint32_t do_usat(int32_t val, int shift)
5544c1
 }
5544c1
 
5544c1
 /* Signed saturate.  */
5544c1
-uint32_t HELPER(ssat)(uint32_t x, uint32_t shift)
5544c1
+uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
5544c1
 {
5544c1
-    return do_ssat(x, shift);
5544c1
+    return do_ssat(env, x, shift);
5544c1
 }
5544c1
 
5544c1
 /* Dual halfword signed saturate.  */
5544c1
-uint32_t HELPER(ssat16)(uint32_t x, uint32_t shift)
5544c1
+uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
5544c1
 {
5544c1
     uint32_t res;
5544c1
 
5544c1
-    res = (uint16_t)do_ssat((int16_t)x, shift);
5544c1
-    res |= do_ssat(((int32_t)x) >> 16, shift) << 16;
5544c1
+    res = (uint16_t)do_ssat(env, (int16_t)x, shift);
5544c1
+    res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
5544c1
     return res;
5544c1
 }
5544c1
 
5544c1
 /* Unsigned saturate.  */
5544c1
-uint32_t HELPER(usat)(uint32_t x, uint32_t shift)
5544c1
+uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
5544c1
 {
5544c1
-    return do_usat(x, shift);
5544c1
+    return do_usat(env, x, shift);
5544c1
 }
5544c1
 
5544c1
 /* Dual halfword unsigned saturate.  */
5544c1
-uint32_t HELPER(usat16)(uint32_t x, uint32_t shift)
5544c1
+uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
5544c1
 {
5544c1
     uint32_t res;
5544c1
 
5544c1
-    res = (uint16_t)do_usat((int16_t)x, shift);
5544c1
-    res |= do_usat(((int32_t)x) >> 16, shift) << 16;
5544c1
+    res = (uint16_t)do_usat(env, (int16_t)x, shift);
5544c1
+    res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
5544c1
     return res;
5544c1
 }
5544c1
 
5544c1
@@ -243,7 +243,7 @@ void HELPER(exception)(CPUARMState *env, uint32_t excp)
5544c1
     cpu_loop_exit(env);
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(cpsr_read)(void)
5544c1
+uint32_t HELPER(cpsr_read)(CPUARMState *env)
5544c1
 {
5544c1
     return cpsr_read(env) & ~CPSR_EXEC;
5544c1
 }
5544c1
@@ -254,7 +254,7 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
5544c1
 }
5544c1
 
5544c1
 /* Access to user mode registers from privileged modes.  */
5544c1
-uint32_t HELPER(get_user_reg)(uint32_t regno)
5544c1
+uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
5544c1
 {
5544c1
     uint32_t val;
5544c1
 
5544c1
@@ -329,7 +329,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
5544c1
    The only way to do that in TCG is a conditional branch, which clobbers
5544c1
    all our temporaries.  For now implement these as helper functions.  */
5544c1
 
5544c1
-uint32_t HELPER (add_cc)(uint32_t a, uint32_t b)
5544c1
+uint32_t HELPER (add_cc)(CPUARMState *env, uint32_t a, uint32_t b)
5544c1
 {
5544c1
     uint32_t result;
5544c1
     result = a + b;
5544c1
@@ -339,7 +339,7 @@ uint32_t HELPER (add_cc)(uint32_t a, uint32_t b)
5544c1
     return result;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
5544c1
+uint32_t HELPER(adc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
5544c1
 {
5544c1
     uint32_t result;
5544c1
     if (!env->CF) {
5544c1
@@ -354,7 +354,7 @@ uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
5544c1
     return result;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
5544c1
+uint32_t HELPER(sub_cc)(CPUARMState *env, uint32_t a, uint32_t b)
5544c1
 {
5544c1
     uint32_t result;
5544c1
     result = a - b;
5544c1
@@ -364,7 +364,7 @@ uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
5544c1
     return result;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b)
5544c1
+uint32_t HELPER(sbc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
5544c1
 {
5544c1
     uint32_t result;
5544c1
     if (!env->CF) {
5544c1
@@ -381,7 +381,7 @@ uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b)
5544c1
 
5544c1
 /* Similarly for variable shift instructions.  */
5544c1
 
5544c1
-uint32_t HELPER(shl)(uint32_t x, uint32_t i)
5544c1
+uint32_t HELPER(shl)(CPUARMState *env, uint32_t x, uint32_t i)
5544c1
 {
5544c1
     int shift = i & 0xff;
5544c1
     if (shift >= 32)
5544c1
@@ -389,7 +389,7 @@ uint32_t HELPER(shl)(uint32_t x, uint32_t i)
5544c1
     return x << shift;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(shr)(uint32_t x, uint32_t i)
5544c1
+uint32_t HELPER(shr)(CPUARMState *env, uint32_t x, uint32_t i)
5544c1
 {
5544c1
     int shift = i & 0xff;
5544c1
     if (shift >= 32)
5544c1
@@ -397,7 +397,7 @@ uint32_t HELPER(shr)(uint32_t x, uint32_t i)
5544c1
     return (uint32_t)x >> shift;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(sar)(uint32_t x, uint32_t i)
5544c1
+uint32_t HELPER(sar)(CPUARMState *env, uint32_t x, uint32_t i)
5544c1
 {
5544c1
     int shift = i & 0xff;
5544c1
     if (shift >= 32)
5544c1
@@ -405,7 +405,7 @@ uint32_t HELPER(sar)(uint32_t x, uint32_t i)
5544c1
     return (int32_t)x >> shift;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
5544c1
+uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
5544c1
 {
5544c1
     int shift = i & 0xff;
5544c1
     if (shift >= 32) {
5544c1
@@ -421,7 +421,7 @@ uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
5544c1
     return x;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
5544c1
+uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
5544c1
 {
5544c1
     int shift = i & 0xff;
5544c1
     if (shift >= 32) {
5544c1
@@ -437,7 +437,7 @@ uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
5544c1
     return x;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
5544c1
+uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
5544c1
 {
5544c1
     int shift = i & 0xff;
5544c1
     if (shift >= 32) {
5544c1
@@ -450,7 +450,7 @@ uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
5544c1
     return x;
5544c1
 }
5544c1
 
5544c1
-uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i)
5544c1
+uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
5544c1
 {
5544c1
     int shift1, shift;
5544c1
     shift1 = i & 0xff;
5544c1
diff --git a/target-arm/translate.c b/target-arm/translate.c
5544c1
index 6f651d9..9ae3b26 100644
5544c1
--- a/target-arm/translate.c
5544c1
+++ b/target-arm/translate.c
5544c1
@@ -490,16 +490,16 @@ static inline void gen_arm_shift_reg(TCGv var, int shiftop,
5544c1
 {
5544c1
     if (flags) {
5544c1
         switch (shiftop) {
5544c1
-        case 0: gen_helper_shl_cc(var, var, shift); break;
5544c1
-        case 1: gen_helper_shr_cc(var, var, shift); break;
5544c1
-        case 2: gen_helper_sar_cc(var, var, shift); break;
5544c1
-        case 3: gen_helper_ror_cc(var, var, shift); break;
5544c1
+        case 0: gen_helper_shl_cc(var, cpu_env, var, shift); break;
5544c1
+        case 1: gen_helper_shr_cc(var, cpu_env, var, shift); break;
5544c1
+        case 2: gen_helper_sar_cc(var, cpu_env, var, shift); break;
5544c1
+        case 3: gen_helper_ror_cc(var, cpu_env, var, shift); break;
5544c1
         }
5544c1
     } else {
5544c1
         switch (shiftop) {
5544c1
-        case 0: gen_helper_shl(var, var, shift); break;
5544c1
-        case 1: gen_helper_shr(var, var, shift); break;
5544c1
-        case 2: gen_helper_sar(var, var, shift); break;
5544c1
+        case 0: gen_helper_shl(var, cpu_env, var, shift); break;
5544c1
+        case 1: gen_helper_shr(var, cpu_env, var, shift); break;
5544c1
+        case 2: gen_helper_sar(var, cpu_env, var, shift); break;
5544c1
         case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
5544c1
                 tcg_gen_rotr_i32(var, var, shift); break;
5544c1
         }
5544c1
@@ -6121,7 +6121,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
5544c1
                 tmp2 = neon_load_reg(rm, 0);
5544c1
                 tmp4 = tcg_const_i32(rn);
5544c1
                 tmp5 = tcg_const_i32(n);
5544c1
-                gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
5544c1
+                gen_helper_neon_tbl(tmp2, cpu_env, tmp2, tmp, tmp4, tmp5);
5544c1
                 tcg_temp_free_i32(tmp);
5544c1
                 if (insn & (1 << 6)) {
5544c1
                     tmp = neon_load_reg(rd, 1);
5544c1
@@ -6130,7 +6130,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
5544c1
                     tcg_gen_movi_i32(tmp, 0);
5544c1
                 }
5544c1
                 tmp3 = neon_load_reg(rm, 1);
5544c1
-                gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
5544c1
+                gen_helper_neon_tbl(tmp3, cpu_env, tmp3, tmp, tmp4, tmp5);
5544c1
                 tcg_temp_free_i32(tmp5);
5544c1
                 tcg_temp_free_i32(tmp4);
5544c1
                 neon_store_reg(rd, 0, tmp2);
5544c1
@@ -6818,7 +6818,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
                     tmp = load_cpu_field(spsr);
5544c1
                 } else {
5544c1
                     tmp = tcg_temp_new_i32();
5544c1
-                    gen_helper_cpsr_read(tmp);
5544c1
+                    gen_helper_cpsr_read(tmp, cpu_env);
5544c1
                 }
5544c1
                 store_reg(s, rd, tmp);
5544c1
             }
5544c1
@@ -6869,11 +6869,11 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
             tmp = load_reg(s, rm);
5544c1
             tmp2 = load_reg(s, rn);
5544c1
             if (op1 & 2)
5544c1
-                gen_helper_double_saturate(tmp2, tmp2);
5544c1
+                gen_helper_double_saturate(tmp2, cpu_env, tmp2);
5544c1
             if (op1 & 1)
5544c1
-                gen_helper_sub_saturate(tmp, tmp, tmp2);
5544c1
+                gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2);
5544c1
             else
5544c1
-                gen_helper_add_saturate(tmp, tmp, tmp2);
5544c1
+                gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
5544c1
             tcg_temp_free_i32(tmp2);
5544c1
             store_reg(s, rd, tmp);
5544c1
             break;
5544c1
@@ -6911,7 +6911,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
                 tcg_temp_free_i64(tmp64);
5544c1
                 if ((sh & 2) == 0) {
5544c1
                     tmp2 = load_reg(s, rn);
5544c1
-                    gen_helper_add_setq(tmp, tmp, tmp2);
5544c1
+                    gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
5544c1
                     tcg_temp_free_i32(tmp2);
5544c1
                 }
5544c1
                 store_reg(s, rd, tmp);
5544c1
@@ -6931,7 +6931,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
                 } else {
5544c1
                     if (op1 == 0) {
5544c1
                         tmp2 = load_reg(s, rn);
5544c1
-                        gen_helper_add_setq(tmp, tmp, tmp2);
5544c1
+                        gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
5544c1
                         tcg_temp_free_i32(tmp2);
5544c1
                     }
5544c1
                     store_reg(s, rd, tmp);
5544c1
@@ -7005,11 +7005,11 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
                 if (IS_USER(s)) {
5544c1
                     goto illegal_op;
5544c1
                 }
5544c1
-                gen_helper_sub_cc(tmp, tmp, tmp2);
5544c1
+                gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
5544c1
                 gen_exception_return(s, tmp);
5544c1
             } else {
5544c1
                 if (set_cc) {
5544c1
-                    gen_helper_sub_cc(tmp, tmp, tmp2);
5544c1
+                    gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
5544c1
                 } else {
5544c1
                     tcg_gen_sub_i32(tmp, tmp, tmp2);
5544c1
                 }
5544c1
@@ -7018,7 +7018,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
             break;
5544c1
         case 0x03:
5544c1
             if (set_cc) {
5544c1
-                gen_helper_sub_cc(tmp, tmp2, tmp);
5544c1
+                gen_helper_sub_cc(tmp, cpu_env, tmp2, tmp);
5544c1
             } else {
5544c1
                 tcg_gen_sub_i32(tmp, tmp2, tmp);
5544c1
             }
5544c1
@@ -7026,7 +7026,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
             break;
5544c1
         case 0x04:
5544c1
             if (set_cc) {
5544c1
-                gen_helper_add_cc(tmp, tmp, tmp2);
5544c1
+                gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
5544c1
             } else {
5544c1
                 tcg_gen_add_i32(tmp, tmp, tmp2);
5544c1
             }
5544c1
@@ -7034,7 +7034,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
             break;
5544c1
         case 0x05:
5544c1
             if (set_cc) {
5544c1
-                gen_helper_adc_cc(tmp, tmp, tmp2);
5544c1
+                gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
5544c1
             } else {
5544c1
                 gen_add_carry(tmp, tmp, tmp2);
5544c1
             }
5544c1
@@ -7042,7 +7042,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
             break;
5544c1
         case 0x06:
5544c1
             if (set_cc) {
5544c1
-                gen_helper_sbc_cc(tmp, tmp, tmp2);
5544c1
+                gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
5544c1
             } else {
5544c1
                 gen_sub_carry(tmp, tmp, tmp2);
5544c1
             }
5544c1
@@ -7050,7 +7050,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
             break;
5544c1
         case 0x07:
5544c1
             if (set_cc) {
5544c1
-                gen_helper_sbc_cc(tmp, tmp2, tmp);
5544c1
+                gen_helper_sbc_cc(tmp, cpu_env, tmp2, tmp);
5544c1
             } else {
5544c1
                 gen_sub_carry(tmp, tmp2, tmp);
5544c1
             }
5544c1
@@ -7072,13 +7072,13 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
             break;
5544c1
         case 0x0a:
5544c1
             if (set_cc) {
5544c1
-                gen_helper_sub_cc(tmp, tmp, tmp2);
5544c1
+                gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
5544c1
             }
5544c1
             tcg_temp_free_i32(tmp);
5544c1
             break;
5544c1
         case 0x0b:
5544c1
             if (set_cc) {
5544c1
-                gen_helper_add_cc(tmp, tmp, tmp2);
5544c1
+                gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
5544c1
             }
5544c1
             tcg_temp_free_i32(tmp);
5544c1
             break;
5544c1
@@ -7395,9 +7395,9 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
                         sh = (insn >> 16) & 0x1f;
5544c1
                         tmp2 = tcg_const_i32(sh);
5544c1
                         if (insn & (1 << 22))
5544c1
-                          gen_helper_usat(tmp, tmp, tmp2);
5544c1
+                          gen_helper_usat(tmp, cpu_env, tmp, tmp2);
5544c1
                         else
5544c1
-                          gen_helper_ssat(tmp, tmp, tmp2);
5544c1
+                          gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
5544c1
                         tcg_temp_free_i32(tmp2);
5544c1
                         store_reg(s, rd, tmp);
5544c1
                     } else if ((insn & 0x00300fe0) == 0x00200f20) {
5544c1
@@ -7406,9 +7406,9 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
                         sh = (insn >> 16) & 0x1f;
5544c1
                         tmp2 = tcg_const_i32(sh);
5544c1
                         if (insn & (1 << 22))
5544c1
-                          gen_helper_usat16(tmp, tmp, tmp2);
5544c1
+                          gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
5544c1
                         else
5544c1
-                          gen_helper_ssat16(tmp, tmp, tmp2);
5544c1
+                          gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
5544c1
                         tcg_temp_free_i32(tmp2);
5544c1
                         store_reg(s, rd, tmp);
5544c1
                     } else if ((insn & 0x00700fe0) == 0x00000fa0) {
5544c1
@@ -7518,7 +7518,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
                              * however it may overflow considered as a signed
5544c1
                              * operation, in which case we must set the Q flag.
5544c1
                              */
5544c1
-                            gen_helper_add_setq(tmp, tmp, tmp2);
5544c1
+                            gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
5544c1
                         }
5544c1
                         tcg_temp_free_i32(tmp2);
5544c1
                         if (insn & (1 << 22)) {
5544c1
@@ -7534,7 +7534,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
                             if (rd != 15)
5544c1
                               {
5544c1
                                 tmp2 = load_reg(s, rd);
5544c1
-                                gen_helper_add_setq(tmp, tmp, tmp2);
5544c1
+                                gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
5544c1
                                 tcg_temp_free_i32(tmp2);
5544c1
                               }
5544c1
                             store_reg(s, rn, tmp);
5544c1
@@ -7738,7 +7738,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
5544c1
                             } else if (user) {
5544c1
                                 tmp = tcg_temp_new_i32();
5544c1
                                 tmp2 = tcg_const_i32(i);
5544c1
-                                gen_helper_get_user_reg(tmp, tmp2);
5544c1
+                                gen_helper_get_user_reg(tmp, cpu_env, tmp2);
5544c1
                                 tcg_temp_free_i32(tmp2);
5544c1
                             } else {
5544c1
                                 tmp = load_reg(s, i);
5544c1
@@ -7865,31 +7865,31 @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCG
5544c1
         break;
5544c1
     case 8: /* add */
5544c1
         if (conds)
5544c1
-            gen_helper_add_cc(t0, t0, t1);
5544c1
+            gen_helper_add_cc(t0, cpu_env, t0, t1);
5544c1
         else
5544c1
             tcg_gen_add_i32(t0, t0, t1);
5544c1
         break;
5544c1
     case 10: /* adc */
5544c1
         if (conds)
5544c1
-            gen_helper_adc_cc(t0, t0, t1);
5544c1
+            gen_helper_adc_cc(t0, cpu_env, t0, t1);
5544c1
         else
5544c1
             gen_adc(t0, t1);
5544c1
         break;
5544c1
     case 11: /* sbc */
5544c1
         if (conds)
5544c1
-            gen_helper_sbc_cc(t0, t0, t1);
5544c1
+            gen_helper_sbc_cc(t0, cpu_env, t0, t1);
5544c1
         else
5544c1
             gen_sub_carry(t0, t0, t1);
5544c1
         break;
5544c1
     case 13: /* sub */
5544c1
         if (conds)
5544c1
-            gen_helper_sub_cc(t0, t0, t1);
5544c1
+            gen_helper_sub_cc(t0, cpu_env, t0, t1);
5544c1
         else
5544c1
             tcg_gen_sub_i32(t0, t0, t1);
5544c1
         break;
5544c1
     case 14: /* rsb */
5544c1
         if (conds)
5544c1
-            gen_helper_sub_cc(t0, t1, t0);
5544c1
+            gen_helper_sub_cc(t0, cpu_env, t1, t0);
5544c1
         else
5544c1
             tcg_gen_sub_i32(t0, t1, t0);
5544c1
         break;
5544c1
@@ -8111,7 +8111,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
5544c1
                     gen_st32(tmp, addr, 0);
5544c1
                     tcg_gen_addi_i32(addr, addr, 4);
5544c1
                     tmp = tcg_temp_new_i32();
5544c1
-                    gen_helper_cpsr_read(tmp);
5544c1
+                    gen_helper_cpsr_read(tmp, cpu_env);
5544c1
                     gen_st32(tmp, addr, 0);
5544c1
                     if (insn & (1 << 21)) {
5544c1
                         if ((insn & (1 << 24)) == 0) {
5544c1
@@ -8293,11 +8293,11 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
5544c1
                 tmp = load_reg(s, rn);
5544c1
                 tmp2 = load_reg(s, rm);
5544c1
                 if (op & 1)
5544c1
-                    gen_helper_double_saturate(tmp, tmp);
5544c1
+                    gen_helper_double_saturate(tmp, cpu_env, tmp);
5544c1
                 if (op & 2)
5544c1
-                    gen_helper_sub_saturate(tmp, tmp2, tmp);
5544c1
+                    gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp);
5544c1
                 else
5544c1
-                    gen_helper_add_saturate(tmp, tmp, tmp2);
5544c1
+                    gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
5544c1
                 tcg_temp_free_i32(tmp2);
5544c1
             } else {
5544c1
                 tmp = load_reg(s, rn);
5544c1
@@ -8353,7 +8353,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
5544c1
                 tcg_temp_free_i32(tmp2);
5544c1
                 if (rs != 15) {
5544c1
                     tmp2 = load_reg(s, rs);
5544c1
-                    gen_helper_add_setq(tmp, tmp, tmp2);
5544c1
+                    gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
5544c1
                     tcg_temp_free_i32(tmp2);
5544c1
                 }
5544c1
                 break;
5544c1
@@ -8370,13 +8370,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
5544c1
                      * however it may overflow considered as a signed
5544c1
                      * operation, in which case we must set the Q flag.
5544c1
                      */
5544c1
-                    gen_helper_add_setq(tmp, tmp, tmp2);
5544c1
+                    gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
5544c1
                 }
5544c1
                 tcg_temp_free_i32(tmp2);
5544c1
                 if (rs != 15)
5544c1
                   {
5544c1
                     tmp2 = load_reg(s, rs);
5544c1
-                    gen_helper_add_setq(tmp, tmp, tmp2);
5544c1
+                    gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
5544c1
                     tcg_temp_free_i32(tmp2);
5544c1
                   }
5544c1
                 break;
5544c1
@@ -8393,7 +8393,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
5544c1
                 if (rs != 15)
5544c1
                   {
5544c1
                     tmp2 = load_reg(s, rs);
5544c1
-                    gen_helper_add_setq(tmp, tmp, tmp2);
5544c1
+                    gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
5544c1
                     tcg_temp_free_i32(tmp2);
5544c1
                   }
5544c1
                 break;
5544c1
@@ -8632,7 +8632,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
5544c1
                             gen_helper_v7m_mrs(tmp, cpu_env, addr);
5544c1
                             tcg_temp_free_i32(addr);
5544c1
                         } else {
5544c1
-                            gen_helper_cpsr_read(tmp);
5544c1
+                            gen_helper_cpsr_read(tmp, cpu_env);
5544c1
                         }
5544c1
                         store_reg(s, rd, tmp);
5544c1
                         break;
5544c1
@@ -8721,15 +8721,15 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
5544c1
                         if (op & 4) {
5544c1
                             /* Unsigned.  */
5544c1
                             if ((op & 1) && shift == 0)
5544c1
-                                gen_helper_usat16(tmp, tmp, tmp2);
5544c1
+                                gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
5544c1
                             else
5544c1
-                                gen_helper_usat(tmp, tmp, tmp2);
5544c1
+                                gen_helper_usat(tmp, cpu_env, tmp, tmp2);
5544c1
                         } else {
5544c1
                             /* Signed.  */
5544c1
                             if ((op & 1) && shift == 0)
5544c1
-                                gen_helper_ssat16(tmp, tmp, tmp2);
5544c1
+                                gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
5544c1
                             else
5544c1
-                                gen_helper_ssat(tmp, tmp, tmp2);
5544c1
+                                gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
5544c1
                         }
5544c1
                         tcg_temp_free_i32(tmp2);
5544c1
                         break;
5544c1
@@ -9017,12 +9017,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
5544c1
                 if (s->condexec_mask)
5544c1
                     tcg_gen_sub_i32(tmp, tmp, tmp2);
5544c1
                 else
5544c1
-                    gen_helper_sub_cc(tmp, tmp, tmp2);
5544c1
+                    gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
5544c1
             } else {
5544c1
                 if (s->condexec_mask)
5544c1
                     tcg_gen_add_i32(tmp, tmp, tmp2);
5544c1
                 else
5544c1
-                    gen_helper_add_cc(tmp, tmp, tmp2);
5544c1
+                    gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
5544c1
             }
5544c1
             tcg_temp_free_i32(tmp2);
5544c1
             store_reg(s, rd, tmp);
5544c1
@@ -9053,7 +9053,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
5544c1
             tcg_gen_movi_i32(tmp2, insn & 0xff);
5544c1
             switch (op) {
5544c1
             case 1: /* cmp */
5544c1
-                gen_helper_sub_cc(tmp, tmp, tmp2);
5544c1
+                gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
5544c1
                 tcg_temp_free_i32(tmp);
5544c1
                 tcg_temp_free_i32(tmp2);
5544c1
                 break;
5544c1
@@ -9061,7 +9061,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
5544c1
                 if (s->condexec_mask)
5544c1
                     tcg_gen_add_i32(tmp, tmp, tmp2);
5544c1
                 else
5544c1
-                    gen_helper_add_cc(tmp, tmp, tmp2);
5544c1
+                    gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
5544c1
                 tcg_temp_free_i32(tmp2);
5544c1
                 store_reg(s, rd, tmp);
5544c1
                 break;
5544c1
@@ -9069,7 +9069,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
5544c1
                 if (s->condexec_mask)
5544c1
                     tcg_gen_sub_i32(tmp, tmp, tmp2);
5544c1
                 else
5544c1
-                    gen_helper_sub_cc(tmp, tmp, tmp2);
5544c1
+                    gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
5544c1
                 tcg_temp_free_i32(tmp2);
5544c1
                 store_reg(s, rd, tmp);
5544c1
                 break;
5544c1
@@ -9105,7 +9105,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
5544c1
             case 1: /* cmp */
5544c1
                 tmp = load_reg(s, rd);
5544c1
                 tmp2 = load_reg(s, rm);
5544c1
-                gen_helper_sub_cc(tmp, tmp, tmp2);
5544c1
+                gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
5544c1
                 tcg_temp_free_i32(tmp2);
5544c1
                 tcg_temp_free_i32(tmp);
5544c1
                 break;
5544c1
@@ -9166,25 +9166,25 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
5544c1
             break;
5544c1
         case 0x2: /* lsl */
5544c1
             if (s->condexec_mask) {
5544c1
-                gen_helper_shl(tmp2, tmp2, tmp);
5544c1
+                gen_helper_shl(tmp2, cpu_env, tmp2, tmp);
5544c1
             } else {
5544c1
-                gen_helper_shl_cc(tmp2, tmp2, tmp);
5544c1
+                gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp);
5544c1
                 gen_logic_CC(tmp2);
5544c1
             }
5544c1
             break;
5544c1
         case 0x3: /* lsr */
5544c1
             if (s->condexec_mask) {
5544c1
-                gen_helper_shr(tmp2, tmp2, tmp);
5544c1
+                gen_helper_shr(tmp2, cpu_env, tmp2, tmp);
5544c1
             } else {
5544c1
-                gen_helper_shr_cc(tmp2, tmp2, tmp);
5544c1
+                gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp);
5544c1
                 gen_logic_CC(tmp2);
5544c1
             }
5544c1
             break;
5544c1
         case 0x4: /* asr */
5544c1
             if (s->condexec_mask) {
5544c1
-                gen_helper_sar(tmp2, tmp2, tmp);
5544c1
+                gen_helper_sar(tmp2, cpu_env, tmp2, tmp);
5544c1
             } else {
5544c1
-                gen_helper_sar_cc(tmp2, tmp2, tmp);
5544c1
+                gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp);
5544c1
                 gen_logic_CC(tmp2);
5544c1
             }
5544c1
             break;
5544c1
@@ -9192,20 +9192,20 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
5544c1
             if (s->condexec_mask)
5544c1
                 gen_adc(tmp, tmp2);
5544c1
             else
5544c1
-                gen_helper_adc_cc(tmp, tmp, tmp2);
5544c1
+                gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
5544c1
             break;
5544c1
         case 0x6: /* sbc */
5544c1
             if (s->condexec_mask)
5544c1
                 gen_sub_carry(tmp, tmp, tmp2);
5544c1
             else
5544c1
-                gen_helper_sbc_cc(tmp, tmp, tmp2);
5544c1
+                gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
5544c1
             break;
5544c1
         case 0x7: /* ror */
5544c1
             if (s->condexec_mask) {
5544c1
                 tcg_gen_andi_i32(tmp, tmp, 0x1f);
5544c1
                 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
5544c1
             } else {
5544c1
-                gen_helper_ror_cc(tmp2, tmp2, tmp);
5544c1
+                gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp);
5544c1
                 gen_logic_CC(tmp2);
5544c1
             }
5544c1
             break;
5544c1
@@ -9218,14 +9218,14 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
5544c1
             if (s->condexec_mask)
5544c1
                 tcg_gen_neg_i32(tmp, tmp2);
5544c1
             else
5544c1
-                gen_helper_sub_cc(tmp, tmp, tmp2);
5544c1
+                gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
5544c1
             break;
5544c1
         case 0xa: /* cmp */
5544c1
-            gen_helper_sub_cc(tmp, tmp, tmp2);
5544c1
+            gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
5544c1
             rd = 16;
5544c1
             break;
5544c1
         case 0xb: /* cmn */
5544c1
-            gen_helper_add_cc(tmp, tmp, tmp2);
5544c1
+            gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
5544c1
             rd = 16;
5544c1
             break;
5544c1
         case 0xc: /* orr */
5544c1
-- 
5544c1
1.7.12.1
5544c1