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Blame 0012-cris-Handle-conditional-stores-on-CRISv10.patch

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From 3e8088148bb56b84a739c2ef3c63d89188a1ad8f Mon Sep 17 00:00:00 2001
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From: Stefan Sandstrom <Stefan.Sandstrom@axis.com>
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Date: Mon, 12 Dec 2011 11:38:31 +0100
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Subject: [PATCH 12/25] cris: Handle conditional stores on CRISv10
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Signed-off-by: Stefan Sandstrom <Stefan.Sandstrom@axis.com>
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Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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---
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 target-cris/cpu.h           |    2 +
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 target-cris/helper.c        |    1 +
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 target-cris/translate_v10.c |   72 +++++++++++++++++++++++++++++++++++++++---
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 3 files changed, 69 insertions(+), 6 deletions(-)
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diff --git a/target-cris/cpu.h b/target-cris/cpu.h
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index 8ae0ce3..453afbb 100644
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--- a/target-cris/cpu.h
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+++ b/target-cris/cpu.h
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@@ -67,6 +67,8 @@
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 #define Q_FLAG 0x80000000
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 #define M_FLAG 0x40000000
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 #define PFIX_FLAG 0x800      /* CRISv10 Only.  */
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+#define F_FLAG_V10 0x400
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+#define P_FLAG_V10 0x200
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 #define S_FLAG 0x200
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 #define R_FLAG 0x100
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 #define P_FLAG 0x80
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diff --git a/target-cris/helper.c b/target-cris/helper.c
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index 75f0035..5bc6d81 100644
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--- a/target-cris/helper.c
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+++ b/target-cris/helper.c
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@@ -157,6 +157,7 @@ static void do_interruptv10(CPUState *env)
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 	/* Now that we are in kernel mode, load the handlers address.  */
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 	env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
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 	env->locked_irq = 1;
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+	env->pregs[PR_CCS] |= F_FLAG_V10; /* set F.  */
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 	qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", 
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 		      __func__, env->pc, ex_vec, 
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diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
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index 637ac20..95053b6 100644
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--- a/target-cris/translate_v10.c
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+++ b/target-cris/translate_v10.c
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@@ -62,6 +62,65 @@ static inline void cris_illegal_insn(DisasContext *dc)
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     t_gen_raise_exception(EXCP_BREAK);
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 }
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+static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
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+                       unsigned int size, int mem_index)
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+{
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+    int l1 = gen_new_label();
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+    TCGv taddr = tcg_temp_local_new();
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+    TCGv tval = tcg_temp_local_new();
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+    TCGv t1 = tcg_temp_local_new();
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+    dc->postinc = 0;
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+    cris_evaluate_flags(dc);
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+
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+    tcg_gen_mov_tl(taddr, addr);
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+    tcg_gen_mov_tl(tval, val);
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+
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+    /* Store only if F flag isn't set */
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+    tcg_gen_andi_tl(t1, cpu_PR[PR_CCS], F_FLAG_V10);
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+    tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
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+    if (size == 1) {
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+        tcg_gen_qemu_st8(tval, taddr, mem_index);
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+    } else if (size == 2) {
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+        tcg_gen_qemu_st16(tval, taddr, mem_index);
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+    } else {
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+        tcg_gen_qemu_st32(tval, taddr, mem_index);
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+    }
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+    gen_set_label(l1);
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+    tcg_gen_shri_tl(t1, t1, 1);  /* shift F to P position */
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+    tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=F*/
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+    tcg_temp_free(t1);
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+    tcg_temp_free(tval);
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+    tcg_temp_free(taddr);
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+}
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+
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+static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
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+                       unsigned int size)
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+{
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+    int mem_index = cpu_mmu_index(dc->env);
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+
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+    /* If we get a fault on a delayslot we must keep the jmp state in
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+       the cpu-state to be able to re-execute the jmp.  */
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+    if (dc->delayed_branch == 1) {
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+        cris_store_direct_jmp(dc);
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+    }
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+
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+    /* Conditional writes. We only support the kind were X is known
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+       at translation time.  */
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+    if (dc->flagx_known && dc->flags_x) {
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+        gen_store_v10_conditional(dc, addr, val, size, mem_index);
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+        return;
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+    }
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+
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+    if (size == 1) {
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+        tcg_gen_qemu_st8(val, addr, mem_index);
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+    } else if (size == 2) {
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+        tcg_gen_qemu_st16(val, addr, mem_index);
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+    } else {
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+        tcg_gen_qemu_st32(val, addr, mem_index);
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+    }
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+}
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+
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+
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 /* Prefix flag and register are used to handle the more complex
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    addressing modes.  */
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 static void cris_set_prefix(DisasContext *dc)
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@@ -313,7 +372,8 @@ static unsigned int dec10_setclrf(DisasContext *dc)
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     if (set) {
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         tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
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     } else {
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-        tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
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+        tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS],
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+                        ~(flags|F_FLAG_V10|P_FLAG_V10));
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     }
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     dc->flags_uptodate = 1;
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@@ -723,7 +783,7 @@ static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size)
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     LOG_DIS("move.%d $r%d, [$r%d]\n", dc->size, dc->src, dc->dst);
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     addr = tcg_temp_new();
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     crisv10_prepare_memaddr(dc, addr, size);
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-    gen_store(dc, addr, cpu_R[dc->dst], size);
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+    gen_store_v10(dc, addr, cpu_R[dc->dst], size);
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     insn_len += crisv10_post_memaddr(dc, size);
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     return insn_len;
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@@ -767,10 +827,10 @@ static unsigned int dec10_ind_move_pr_m(DisasContext *dc)
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         t0 = tcg_temp_new();
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         cris_evaluate_flags(dc);
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         tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG);
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-        gen_store(dc, addr, t0, size);
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+        gen_store_v10(dc, addr, t0, size);
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         tcg_temp_free(t0);
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     } else {
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-        gen_store(dc, addr, cpu_PR[dc->dst], size);
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+        gen_store_v10(dc, addr, cpu_PR[dc->dst], size);
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     }
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     t0 = tcg_temp_new();
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     insn_len += crisv10_post_memaddr(dc, size);
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@@ -793,9 +853,9 @@ static void dec10_movem_r_m(DisasContext *dc)
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     tcg_gen_mov_tl(t0, addr);
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     for (i = dc->dst; i >= 0; i--) {
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         if ((pfix && dc->mode == CRISV10_MODE_AUTOINC) && dc->src == i) {
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-            gen_store(dc, addr, t0, 4);
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+            gen_store_v10(dc, addr, t0, 4);
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         } else {
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-            gen_store(dc, addr, cpu_R[i], 4);
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+            gen_store_v10(dc, addr, cpu_R[i], 4);
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         }
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         tcg_gen_addi_tl(addr, addr, 4);
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     }
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-- 
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1.7.7.5
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