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From 3eb9b25ae5d2bcc024646c5a04f28899661ab14c Mon Sep 17 00:00:00 2001
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From: Blue Swirl <blauwirbel@gmail.com>
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Date: Sun, 2 Sep 2012 07:33:31 +0000
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Subject: [PATCH] target-s390x: split FPU ops
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Move floating point instructions to fpu_helper.c.
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While exporting some condition code helpers,
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avoid duplicate identifier conflict with translate.c.
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Remove unused set_cc_nz_f64() in translate.c.
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Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Signed-off-by: Alexander Graf <agraf@suse.de>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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target-s390x/Makefile.objs | 2 +
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target-s390x/cpu.h | 6 +
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target-s390x/fpu_helper.c | 836 +++++++++++++++++++++++++++++++++++++++++++++
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target-s390x/op_helper.c | 802 -------------------------------------------
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target-s390x/translate.c | 11 +-
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5 files changed, 847 insertions(+), 810 deletions(-)
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create mode 100644 target-s390x/fpu_helper.c
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diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
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index 80be3bb..23b3bd9 100644
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--- a/target-s390x/Makefile.objs
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+++ b/target-s390x/Makefile.objs
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@@ -1,5 +1,7 @@
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obj-y += translate.o op_helper.o helper.o cpu.o interrupt.o
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+obj-y += fpu_helper.o
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obj-$(CONFIG_SOFTMMU) += machine.o
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obj-$(CONFIG_KVM) += kvm.o
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$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
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+$(obj)/fpu_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
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diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
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index 18ac6e3..b4620c5 100644
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--- a/target-s390x/cpu.h
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+++ b/target-s390x/cpu.h
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@@ -999,4 +999,10 @@ static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
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env->psw.addr = tb->pc;
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}
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+/* fpu_helper.c */
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+uint32_t set_cc_f32(float32 v1, float32 v2);
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+uint32_t set_cc_f64(float64 v1, float64 v2);
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+uint32_t set_cc_nz_f32(float32 v);
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+uint32_t set_cc_nz_f64(float64 v);
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+
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#endif
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diff --git a/target-s390x/fpu_helper.c b/target-s390x/fpu_helper.c
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new file mode 100644
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index 0000000..1389052
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--- /dev/null
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+++ b/target-s390x/fpu_helper.c
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@@ -0,0 +1,836 @@
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+/*
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+ * S/390 FPU helper routines
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+ *
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+ * Copyright (c) 2009 Ulrich Hecht
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+ * Copyright (c) 2009 Alexander Graf
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+ *
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+ * This library is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU Lesser General Public
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+ * License as published by the Free Software Foundation; either
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+ * version 2 of the License, or (at your option) any later version.
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+ *
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+ * This library is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ * Lesser General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU Lesser General Public
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+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#include "cpu.h"
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+#include "dyngen-exec.h"
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+#include "helper.h"
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+
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+#if !defined(CONFIG_USER_ONLY)
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+#include "softmmu_exec.h"
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+#endif
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+
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+/* #define DEBUG_HELPER */
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+#ifdef DEBUG_HELPER
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+#define HELPER_LOG(x...) qemu_log(x)
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+#else
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+#define HELPER_LOG(x...)
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+#endif
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+
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+static inline int float_comp_to_cc(int float_compare)
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+{
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+ switch (float_compare) {
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+ case float_relation_equal:
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+ return 0;
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+ case float_relation_less:
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+ return 1;
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+ case float_relation_greater:
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+ return 2;
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+ case float_relation_unordered:
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+ return 3;
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+ default:
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+ cpu_abort(env, "unknown return value for float compare\n");
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+ }
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+}
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+
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+/* condition codes for binary FP ops */
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+uint32_t set_cc_f32(float32 v1, float32 v2)
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+{
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+ return float_comp_to_cc(float32_compare_quiet(v1, v2, &env->fpu_status));
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+}
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+
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+uint32_t set_cc_f64(float64 v1, float64 v2)
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+{
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+ return float_comp_to_cc(float64_compare_quiet(v1, v2, &env->fpu_status));
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+}
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+
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+/* condition codes for unary FP ops */
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+uint32_t set_cc_nz_f32(float32 v)
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+{
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+ if (float32_is_any_nan(v)) {
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+ return 3;
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+ } else if (float32_is_zero(v)) {
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+ return 0;
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+ } else if (float32_is_neg(v)) {
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+ return 1;
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+ } else {
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+ return 2;
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+ }
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+}
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+
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+uint32_t set_cc_nz_f64(float64 v)
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+{
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+ if (float64_is_any_nan(v)) {
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+ return 3;
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+ } else if (float64_is_zero(v)) {
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+ return 0;
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+ } else if (float64_is_neg(v)) {
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+ return 1;
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+ } else {
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+ return 2;
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+ }
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+}
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+
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+static uint32_t set_cc_nz_f128(float128 v)
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+{
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+ if (float128_is_any_nan(v)) {
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+ return 3;
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+ } else if (float128_is_zero(v)) {
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+ return 0;
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+ } else if (float128_is_neg(v)) {
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+ return 1;
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+ } else {
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+ return 2;
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+ }
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+}
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+
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+/* convert 32-bit int to 64-bit float */
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+void HELPER(cdfbr)(uint32_t f1, int32_t v2)
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+{
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+ HELPER_LOG("%s: converting %d to f%d\n", __func__, v2, f1);
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+ env->fregs[f1].d = int32_to_float64(v2, &env->fpu_status);
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+}
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+
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+/* convert 32-bit int to 128-bit float */
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+void HELPER(cxfbr)(uint32_t f1, int32_t v2)
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+{
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+ CPU_QuadU v1;
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+
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+ v1.q = int32_to_float128(v2, &env->fpu_status);
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+ env->fregs[f1].ll = v1.ll.upper;
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+ env->fregs[f1 + 2].ll = v1.ll.lower;
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+}
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+
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+/* convert 64-bit int to 32-bit float */
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+void HELPER(cegbr)(uint32_t f1, int64_t v2)
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+{
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+ HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
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+ env->fregs[f1].l.upper = int64_to_float32(v2, &env->fpu_status);
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+}
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+
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+/* convert 64-bit int to 64-bit float */
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+void HELPER(cdgbr)(uint32_t f1, int64_t v2)
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+{
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+ HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
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+ env->fregs[f1].d = int64_to_float64(v2, &env->fpu_status);
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+}
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+
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+/* convert 64-bit int to 128-bit float */
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+void HELPER(cxgbr)(uint32_t f1, int64_t v2)
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+{
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+ CPU_QuadU x1;
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+
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+ x1.q = int64_to_float128(v2, &env->fpu_status);
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+ HELPER_LOG("%s: converted %ld to 0x%lx and 0x%lx\n", __func__, v2,
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+ x1.ll.upper, x1.ll.lower);
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+ env->fregs[f1].ll = x1.ll.upper;
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+ env->fregs[f1 + 2].ll = x1.ll.lower;
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+}
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+
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+/* convert 32-bit int to 32-bit float */
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+void HELPER(cefbr)(uint32_t f1, int32_t v2)
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+{
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+ env->fregs[f1].l.upper = int32_to_float32(v2, &env->fpu_status);
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+ HELPER_LOG("%s: converting %d to 0x%d in f%d\n", __func__, v2,
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+ env->fregs[f1].l.upper, f1);
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+}
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+
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+/* 32-bit FP addition RR */
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+uint32_t HELPER(aebr)(uint32_t f1, uint32_t f2)
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+{
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+ env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
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+ env->fregs[f2].l.upper,
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+ &env->fpu_status);
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+ HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
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+ env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
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+
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+ return set_cc_nz_f32(env->fregs[f1].l.upper);
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+}
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+
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+/* 64-bit FP addition RR */
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+uint32_t HELPER(adbr)(uint32_t f1, uint32_t f2)
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+{
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+ env->fregs[f1].d = float64_add(env->fregs[f1].d, env->fregs[f2].d,
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+ &env->fpu_status);
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+ HELPER_LOG("%s: adding 0x%ld resulting in 0x%ld in f%d\n", __func__,
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+ env->fregs[f2].d, env->fregs[f1].d, f1);
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+
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+ return set_cc_nz_f64(env->fregs[f1].d);
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+}
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+
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+/* 32-bit FP subtraction RR */
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+uint32_t HELPER(sebr)(uint32_t f1, uint32_t f2)
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+{
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+ env->fregs[f1].l.upper = float32_sub(env->fregs[f1].l.upper,
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+ env->fregs[f2].l.upper,
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+ &env->fpu_status);
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+ HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
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+ env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
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+
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+ return set_cc_nz_f32(env->fregs[f1].l.upper);
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+}
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+
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5544c1 |
+/* 64-bit FP subtraction RR */
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+uint32_t HELPER(sdbr)(uint32_t f1, uint32_t f2)
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+{
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5544c1 |
+ env->fregs[f1].d = float64_sub(env->fregs[f1].d, env->fregs[f2].d,
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+ &env->fpu_status);
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+ HELPER_LOG("%s: subtracting 0x%ld resulting in 0x%ld in f%d\n",
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5544c1 |
+ __func__, env->fregs[f2].d, env->fregs[f1].d, f1);
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+
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+ return set_cc_nz_f64(env->fregs[f1].d);
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5544c1 |
+}
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+
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5544c1 |
+/* 32-bit FP division RR */
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5544c1 |
+void HELPER(debr)(uint32_t f1, uint32_t f2)
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5544c1 |
+{
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5544c1 |
+ env->fregs[f1].l.upper = float32_div(env->fregs[f1].l.upper,
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5544c1 |
+ env->fregs[f2].l.upper,
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5544c1 |
+ &env->fpu_status);
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5544c1 |
+}
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+
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5544c1 |
+/* 128-bit FP division RR */
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5544c1 |
+void HELPER(dxbr)(uint32_t f1, uint32_t f2)
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5544c1 |
+{
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+ CPU_QuadU v1;
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+ CPU_QuadU v2;
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5544c1 |
+ CPU_QuadU res;
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+
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5544c1 |
+ v1.ll.upper = env->fregs[f1].ll;
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+ v1.ll.lower = env->fregs[f1 + 2].ll;
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5544c1 |
+ v2.ll.upper = env->fregs[f2].ll;
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5544c1 |
+ v2.ll.lower = env->fregs[f2 + 2].ll;
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5544c1 |
+ res.q = float128_div(v1.q, v2.q, &env->fpu_status);
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5544c1 |
+ env->fregs[f1].ll = res.ll.upper;
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5544c1 |
+ env->fregs[f1 + 2].ll = res.ll.lower;
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|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 64-bit FP multiplication RR */
|
|
|
5544c1 |
+void HELPER(mdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ env->fregs[f1].d = float64_mul(env->fregs[f1].d, env->fregs[f2].d,
|
|
|
5544c1 |
+ &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 128-bit FP multiplication RR */
|
|
|
5544c1 |
+void HELPER(mxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU v1;
|
|
|
5544c1 |
+ CPU_QuadU v2;
|
|
|
5544c1 |
+ CPU_QuadU res;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v1.ll.upper = env->fregs[f1].ll;
|
|
|
5544c1 |
+ v1.ll.lower = env->fregs[f1 + 2].ll;
|
|
|
5544c1 |
+ v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
+ v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
+ res.q = float128_mul(v1.q, v2.q, &env->fpu_status);
|
|
|
5544c1 |
+ env->fregs[f1].ll = res.ll.upper;
|
|
|
5544c1 |
+ env->fregs[f1 + 2].ll = res.ll.lower;
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* convert 32-bit float to 64-bit float */
|
|
|
5544c1 |
+void HELPER(ldebr)(uint32_t r1, uint32_t r2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ env->fregs[r1].d = float32_to_float64(env->fregs[r2].l.upper,
|
|
|
5544c1 |
+ &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* convert 128-bit float to 64-bit float */
|
|
|
5544c1 |
+void HELPER(ldxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU x2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ x2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
+ x2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
+ env->fregs[f1].d = float128_to_float64(x2.q, &env->fpu_status);
|
|
|
5544c1 |
+ HELPER_LOG("%s: to 0x%ld\n", __func__, env->fregs[f1].d);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* convert 64-bit float to 128-bit float */
|
|
|
5544c1 |
+void HELPER(lxdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU res;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ res.q = float64_to_float128(env->fregs[f2].d, &env->fpu_status);
|
|
|
5544c1 |
+ env->fregs[f1].ll = res.ll.upper;
|
|
|
5544c1 |
+ env->fregs[f1 + 2].ll = res.ll.lower;
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* convert 64-bit float to 32-bit float */
|
|
|
5544c1 |
+void HELPER(ledbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float64 d2 = env->fregs[f2].d;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ env->fregs[f1].l.upper = float64_to_float32(d2, &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* convert 128-bit float to 32-bit float */
|
|
|
5544c1 |
+void HELPER(lexbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU x2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ x2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
+ x2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
+ env->fregs[f1].l.upper = float128_to_float32(x2.q, &env->fpu_status);
|
|
|
5544c1 |
+ HELPER_LOG("%s: to 0x%d\n", __func__, env->fregs[f1].l.upper);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* absolute value of 32-bit float */
|
|
|
5544c1 |
+uint32_t HELPER(lpebr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float32 v1;
|
|
|
5544c1 |
+ float32 v2 = env->fregs[f2].d;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v1 = float32_abs(v2);
|
|
|
5544c1 |
+ env->fregs[f1].d = v1;
|
|
|
5544c1 |
+ return set_cc_nz_f32(v1);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* absolute value of 64-bit float */
|
|
|
5544c1 |
+uint32_t HELPER(lpdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float64 v1;
|
|
|
5544c1 |
+ float64 v2 = env->fregs[f2].d;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v1 = float64_abs(v2);
|
|
|
5544c1 |
+ env->fregs[f1].d = v1;
|
|
|
5544c1 |
+ return set_cc_nz_f64(v1);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* absolute value of 128-bit float */
|
|
|
5544c1 |
+uint32_t HELPER(lpxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU v1;
|
|
|
5544c1 |
+ CPU_QuadU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
+ v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
+ v1.q = float128_abs(v2.q);
|
|
|
5544c1 |
+ env->fregs[f1].ll = v1.ll.upper;
|
|
|
5544c1 |
+ env->fregs[f1 + 2].ll = v1.ll.lower;
|
|
|
5544c1 |
+ return set_cc_nz_f128(v1.q);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* load and test 64-bit float */
|
|
|
5544c1 |
+uint32_t HELPER(ltdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ env->fregs[f1].d = env->fregs[f2].d;
|
|
|
5544c1 |
+ return set_cc_nz_f64(env->fregs[f1].d);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* load and test 32-bit float */
|
|
|
5544c1 |
+uint32_t HELPER(ltebr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ env->fregs[f1].l.upper = env->fregs[f2].l.upper;
|
|
|
5544c1 |
+ return set_cc_nz_f32(env->fregs[f1].l.upper);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* load and test 128-bit float */
|
|
|
5544c1 |
+uint32_t HELPER(ltxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU x;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ x.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
+ x.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
+ env->fregs[f1].ll = x.ll.upper;
|
|
|
5544c1 |
+ env->fregs[f1 + 2].ll = x.ll.lower;
|
|
|
5544c1 |
+ return set_cc_nz_f128(x.q);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* load complement of 32-bit float */
|
|
|
5544c1 |
+uint32_t HELPER(lcebr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ env->fregs[f1].l.upper = float32_chs(env->fregs[f2].l.upper);
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ return set_cc_nz_f32(env->fregs[f1].l.upper);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* load complement of 64-bit float */
|
|
|
5544c1 |
+uint32_t HELPER(lcdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ env->fregs[f1].d = float64_chs(env->fregs[f2].d);
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ return set_cc_nz_f64(env->fregs[f1].d);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* load complement of 128-bit float */
|
|
|
5544c1 |
+uint32_t HELPER(lcxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU x1, x2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ x2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
+ x2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
+ x1.q = float128_chs(x2.q);
|
|
|
5544c1 |
+ env->fregs[f1].ll = x1.ll.upper;
|
|
|
5544c1 |
+ env->fregs[f1 + 2].ll = x1.ll.lower;
|
|
|
5544c1 |
+ return set_cc_nz_f128(x1.q);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 32-bit FP addition RM */
|
|
|
5544c1 |
+void HELPER(aeb)(uint32_t f1, uint32_t val)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float32 v1 = env->fregs[f1].l.upper;
|
|
|
5544c1 |
+ CPU_FloatU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2.l = val;
|
|
|
5544c1 |
+ HELPER_LOG("%s: adding 0x%d from f%d and 0x%d\n", __func__,
|
|
|
5544c1 |
+ v1, f1, v2.f);
|
|
|
5544c1 |
+ env->fregs[f1].l.upper = float32_add(v1, v2.f, &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 32-bit FP division RM */
|
|
|
5544c1 |
+void HELPER(deb)(uint32_t f1, uint32_t val)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float32 v1 = env->fregs[f1].l.upper;
|
|
|
5544c1 |
+ CPU_FloatU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2.l = val;
|
|
|
5544c1 |
+ HELPER_LOG("%s: dividing 0x%d from f%d by 0x%d\n", __func__,
|
|
|
5544c1 |
+ v1, f1, v2.f);
|
|
|
5544c1 |
+ env->fregs[f1].l.upper = float32_div(v1, v2.f, &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 32-bit FP multiplication RM */
|
|
|
5544c1 |
+void HELPER(meeb)(uint32_t f1, uint32_t val)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float32 v1 = env->fregs[f1].l.upper;
|
|
|
5544c1 |
+ CPU_FloatU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2.l = val;
|
|
|
5544c1 |
+ HELPER_LOG("%s: multiplying 0x%d from f%d and 0x%d\n", __func__,
|
|
|
5544c1 |
+ v1, f1, v2.f);
|
|
|
5544c1 |
+ env->fregs[f1].l.upper = float32_mul(v1, v2.f, &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 32-bit FP compare RR */
|
|
|
5544c1 |
+uint32_t HELPER(cebr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float32 v1 = env->fregs[f1].l.upper;
|
|
|
5544c1 |
+ float32 v2 = env->fregs[f2].l.upper;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ HELPER_LOG("%s: comparing 0x%d from f%d and 0x%d\n", __func__,
|
|
|
5544c1 |
+ v1, f1, v2);
|
|
|
5544c1 |
+ return set_cc_f32(v1, v2);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 64-bit FP compare RR */
|
|
|
5544c1 |
+uint32_t HELPER(cdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
+ float64 v2 = env->fregs[f2].d;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%ld\n", __func__,
|
|
|
5544c1 |
+ v1, f1, v2);
|
|
|
5544c1 |
+ return set_cc_f64(v1, v2);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 128-bit FP compare RR */
|
|
|
5544c1 |
+uint32_t HELPER(cxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU v1;
|
|
|
5544c1 |
+ CPU_QuadU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v1.ll.upper = env->fregs[f1].ll;
|
|
|
5544c1 |
+ v1.ll.lower = env->fregs[f1 + 2].ll;
|
|
|
5544c1 |
+ v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
+ v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ return float_comp_to_cc(float128_compare_quiet(v1.q, v2.q,
|
|
|
5544c1 |
+ &env->fpu_status));
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 64-bit FP compare RM */
|
|
|
5544c1 |
+uint32_t HELPER(cdb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
+ CPU_DoubleU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2.ll = ldq(a2);
|
|
|
5544c1 |
+ HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%lx\n", __func__, v1,
|
|
|
5544c1 |
+ f1, v2.d);
|
|
|
5544c1 |
+ return set_cc_f64(v1, v2.d);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 64-bit FP addition RM */
|
|
|
5544c1 |
+uint32_t HELPER(adb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
+ CPU_DoubleU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2.ll = ldq(a2);
|
|
|
5544c1 |
+ HELPER_LOG("%s: adding 0x%lx from f%d and 0x%lx\n", __func__,
|
|
|
5544c1 |
+ v1, f1, v2.d);
|
|
|
5544c1 |
+ env->fregs[f1].d = v1 = float64_add(v1, v2.d, &env->fpu_status);
|
|
|
5544c1 |
+ return set_cc_nz_f64(v1);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 32-bit FP subtraction RM */
|
|
|
5544c1 |
+void HELPER(seb)(uint32_t f1, uint32_t val)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float32 v1 = env->fregs[f1].l.upper;
|
|
|
5544c1 |
+ CPU_FloatU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2.l = val;
|
|
|
5544c1 |
+ env->fregs[f1].l.upper = float32_sub(v1, v2.f, &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 64-bit FP subtraction RM */
|
|
|
5544c1 |
+uint32_t HELPER(sdb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
+ CPU_DoubleU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2.ll = ldq(a2);
|
|
|
5544c1 |
+ env->fregs[f1].d = v1 = float64_sub(v1, v2.d, &env->fpu_status);
|
|
|
5544c1 |
+ return set_cc_nz_f64(v1);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 64-bit FP multiplication RM */
|
|
|
5544c1 |
+void HELPER(mdb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
+ CPU_DoubleU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2.ll = ldq(a2);
|
|
|
5544c1 |
+ HELPER_LOG("%s: multiplying 0x%lx from f%d and 0x%ld\n", __func__,
|
|
|
5544c1 |
+ v1, f1, v2.d);
|
|
|
5544c1 |
+ env->fregs[f1].d = float64_mul(v1, v2.d, &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 64-bit FP division RM */
|
|
|
5544c1 |
+void HELPER(ddb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
+ CPU_DoubleU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2.ll = ldq(a2);
|
|
|
5544c1 |
+ HELPER_LOG("%s: dividing 0x%lx from f%d by 0x%ld\n", __func__,
|
|
|
5544c1 |
+ v1, f1, v2.d);
|
|
|
5544c1 |
+ env->fregs[f1].d = float64_div(v1, v2.d, &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+static void set_round_mode(int m3)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ switch (m3) {
|
|
|
5544c1 |
+ case 0:
|
|
|
5544c1 |
+ /* current mode */
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+ case 1:
|
|
|
5544c1 |
+ /* biased round no nearest */
|
|
|
5544c1 |
+ case 4:
|
|
|
5544c1 |
+ /* round to nearest */
|
|
|
5544c1 |
+ set_float_rounding_mode(float_round_nearest_even, &env->fpu_status);
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+ case 5:
|
|
|
5544c1 |
+ /* round to zero */
|
|
|
5544c1 |
+ set_float_rounding_mode(float_round_to_zero, &env->fpu_status);
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+ case 6:
|
|
|
5544c1 |
+ /* round to +inf */
|
|
|
5544c1 |
+ set_float_rounding_mode(float_round_up, &env->fpu_status);
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+ case 7:
|
|
|
5544c1 |
+ /* round to -inf */
|
|
|
5544c1 |
+ set_float_rounding_mode(float_round_down, &env->fpu_status);
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* convert 32-bit float to 64-bit int */
|
|
|
5544c1 |
+uint32_t HELPER(cgebr)(uint32_t r1, uint32_t f2, uint32_t m3)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float32 v2 = env->fregs[f2].l.upper;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ set_round_mode(m3);
|
|
|
5544c1 |
+ env->regs[r1] = float32_to_int64(v2, &env->fpu_status);
|
|
|
5544c1 |
+ return set_cc_nz_f32(v2);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* convert 64-bit float to 64-bit int */
|
|
|
5544c1 |
+uint32_t HELPER(cgdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float64 v2 = env->fregs[f2].d;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ set_round_mode(m3);
|
|
|
5544c1 |
+ env->regs[r1] = float64_to_int64(v2, &env->fpu_status);
|
|
|
5544c1 |
+ return set_cc_nz_f64(v2);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* convert 128-bit float to 64-bit int */
|
|
|
5544c1 |
+uint32_t HELPER(cgxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
+ v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
+ set_round_mode(m3);
|
|
|
5544c1 |
+ env->regs[r1] = float128_to_int64(v2.q, &env->fpu_status);
|
|
|
5544c1 |
+ if (float128_is_any_nan(v2.q)) {
|
|
|
5544c1 |
+ return 3;
|
|
|
5544c1 |
+ } else if (float128_is_zero(v2.q)) {
|
|
|
5544c1 |
+ return 0;
|
|
|
5544c1 |
+ } else if (float128_is_neg(v2.q)) {
|
|
|
5544c1 |
+ return 1;
|
|
|
5544c1 |
+ } else {
|
|
|
5544c1 |
+ return 2;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* convert 32-bit float to 32-bit int */
|
|
|
5544c1 |
+uint32_t HELPER(cfebr)(uint32_t r1, uint32_t f2, uint32_t m3)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float32 v2 = env->fregs[f2].l.upper;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ set_round_mode(m3);
|
|
|
5544c1 |
+ env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
|
|
|
5544c1 |
+ float32_to_int32(v2, &env->fpu_status);
|
|
|
5544c1 |
+ return set_cc_nz_f32(v2);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* convert 64-bit float to 32-bit int */
|
|
|
5544c1 |
+uint32_t HELPER(cfdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float64 v2 = env->fregs[f2].d;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ set_round_mode(m3);
|
|
|
5544c1 |
+ env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
|
|
|
5544c1 |
+ float64_to_int32(v2, &env->fpu_status);
|
|
|
5544c1 |
+ return set_cc_nz_f64(v2);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* convert 128-bit float to 32-bit int */
|
|
|
5544c1 |
+uint32_t HELPER(cfxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
+ v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
+ env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
|
|
|
5544c1 |
+ float128_to_int32(v2.q, &env->fpu_status);
|
|
|
5544c1 |
+ return set_cc_nz_f128(v2.q);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* load 32-bit FP zero */
|
|
|
5544c1 |
+void HELPER(lzer)(uint32_t f1)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ env->fregs[f1].l.upper = float32_zero;
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* load 64-bit FP zero */
|
|
|
5544c1 |
+void HELPER(lzdr)(uint32_t f1)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ env->fregs[f1].d = float64_zero;
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* load 128-bit FP zero */
|
|
|
5544c1 |
+void HELPER(lzxr)(uint32_t f1)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU x;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ x.q = float64_to_float128(float64_zero, &env->fpu_status);
|
|
|
5544c1 |
+ env->fregs[f1].ll = x.ll.upper;
|
|
|
5544c1 |
+ env->fregs[f1 + 1].ll = x.ll.lower;
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 128-bit FP subtraction RR */
|
|
|
5544c1 |
+uint32_t HELPER(sxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU v1;
|
|
|
5544c1 |
+ CPU_QuadU v2;
|
|
|
5544c1 |
+ CPU_QuadU res;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v1.ll.upper = env->fregs[f1].ll;
|
|
|
5544c1 |
+ v1.ll.lower = env->fregs[f1 + 2].ll;
|
|
|
5544c1 |
+ v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
+ v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
+ res.q = float128_sub(v1.q, v2.q, &env->fpu_status);
|
|
|
5544c1 |
+ env->fregs[f1].ll = res.ll.upper;
|
|
|
5544c1 |
+ env->fregs[f1 + 2].ll = res.ll.lower;
|
|
|
5544c1 |
+ return set_cc_nz_f128(res.q);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 128-bit FP addition RR */
|
|
|
5544c1 |
+uint32_t HELPER(axbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU v1;
|
|
|
5544c1 |
+ CPU_QuadU v2;
|
|
|
5544c1 |
+ CPU_QuadU res;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v1.ll.upper = env->fregs[f1].ll;
|
|
|
5544c1 |
+ v1.ll.lower = env->fregs[f1 + 2].ll;
|
|
|
5544c1 |
+ v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
+ v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
+ res.q = float128_add(v1.q, v2.q, &env->fpu_status);
|
|
|
5544c1 |
+ env->fregs[f1].ll = res.ll.upper;
|
|
|
5544c1 |
+ env->fregs[f1 + 2].ll = res.ll.lower;
|
|
|
5544c1 |
+ return set_cc_nz_f128(res.q);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 32-bit FP multiplication RR */
|
|
|
5544c1 |
+void HELPER(meebr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ env->fregs[f1].l.upper = float32_mul(env->fregs[f1].l.upper,
|
|
|
5544c1 |
+ env->fregs[f2].l.upper,
|
|
|
5544c1 |
+ &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 64-bit FP division RR */
|
|
|
5544c1 |
+void HELPER(ddbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ env->fregs[f1].d = float64_div(env->fregs[f1].d, env->fregs[f2].d,
|
|
|
5544c1 |
+ &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 64-bit FP multiply and add RM */
|
|
|
5544c1 |
+void HELPER(madb)(uint32_t f1, uint64_t a2, uint32_t f3)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_DoubleU v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ HELPER_LOG("%s: f1 %d a2 0x%lx f3 %d\n", __func__, f1, a2, f3);
|
|
|
5544c1 |
+ v2.ll = ldq(a2);
|
|
|
5544c1 |
+ env->fregs[f1].d = float64_add(env->fregs[f1].d,
|
|
|
5544c1 |
+ float64_mul(v2.d, env->fregs[f3].d,
|
|
|
5544c1 |
+ &env->fpu_status),
|
|
|
5544c1 |
+ &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 64-bit FP multiply and add RR */
|
|
|
5544c1 |
+void HELPER(madbr)(uint32_t f1, uint32_t f3, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
|
|
|
5544c1 |
+ env->fregs[f1].d = float64_add(float64_mul(env->fregs[f2].d,
|
|
|
5544c1 |
+ env->fregs[f3].d,
|
|
|
5544c1 |
+ &env->fpu_status),
|
|
|
5544c1 |
+ env->fregs[f1].d, &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 64-bit FP multiply and subtract RR */
|
|
|
5544c1 |
+void HELPER(msdbr)(uint32_t f1, uint32_t f3, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
|
|
|
5544c1 |
+ env->fregs[f1].d = float64_sub(float64_mul(env->fregs[f2].d,
|
|
|
5544c1 |
+ env->fregs[f3].d,
|
|
|
5544c1 |
+ &env->fpu_status),
|
|
|
5544c1 |
+ env->fregs[f1].d, &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* 32-bit FP multiply and add RR */
|
|
|
5544c1 |
+void HELPER(maebr)(uint32_t f1, uint32_t f3, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
|
|
|
5544c1 |
+ float32_mul(env->fregs[f2].l.upper,
|
|
|
5544c1 |
+ env->fregs[f3].l.upper,
|
|
|
5544c1 |
+ &env->fpu_status),
|
|
|
5544c1 |
+ &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* convert 32-bit float to 64-bit float */
|
|
|
5544c1 |
+void HELPER(ldeb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ uint32_t v2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2 = ldl(a2);
|
|
|
5544c1 |
+ env->fregs[f1].d = float32_to_float64(v2,
|
|
|
5544c1 |
+ &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* convert 64-bit float to 128-bit float */
|
|
|
5544c1 |
+void HELPER(lxdb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_DoubleU v2;
|
|
|
5544c1 |
+ CPU_QuadU v1;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v2.ll = ldq(a2);
|
|
|
5544c1 |
+ v1.q = float64_to_float128(v2.d, &env->fpu_status);
|
|
|
5544c1 |
+ env->fregs[f1].ll = v1.ll.upper;
|
|
|
5544c1 |
+ env->fregs[f1 + 2].ll = v1.ll.lower;
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* test data class 32-bit */
|
|
|
5544c1 |
+uint32_t HELPER(tceb)(uint32_t f1, uint64_t m2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float32 v1 = env->fregs[f1].l.upper;
|
|
|
5544c1 |
+ int neg = float32_is_neg(v1);
|
|
|
5544c1 |
+ uint32_t cc = 0;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, (long)v1, m2, neg);
|
|
|
5544c1 |
+ if ((float32_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
|
|
|
5544c1 |
+ (float32_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
|
|
|
5544c1 |
+ (float32_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
|
|
|
5544c1 |
+ (float32_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
|
|
|
5544c1 |
+ cc = 1;
|
|
|
5544c1 |
+ } else if (m2 & (1 << (9-neg))) {
|
|
|
5544c1 |
+ /* assume normalized number */
|
|
|
5544c1 |
+ cc = 1;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ /* FIXME: denormalized? */
|
|
|
5544c1 |
+ return cc;
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* test data class 64-bit */
|
|
|
5544c1 |
+uint32_t HELPER(tcdb)(uint32_t f1, uint64_t m2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
+ int neg = float64_is_neg(v1);
|
|
|
5544c1 |
+ uint32_t cc = 0;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, v1, m2, neg);
|
|
|
5544c1 |
+ if ((float64_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
|
|
|
5544c1 |
+ (float64_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
|
|
|
5544c1 |
+ (float64_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
|
|
|
5544c1 |
+ (float64_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
|
|
|
5544c1 |
+ cc = 1;
|
|
|
5544c1 |
+ } else if (m2 & (1 << (9-neg))) {
|
|
|
5544c1 |
+ /* assume normalized number */
|
|
|
5544c1 |
+ cc = 1;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+ /* FIXME: denormalized? */
|
|
|
5544c1 |
+ return cc;
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* test data class 128-bit */
|
|
|
5544c1 |
+uint32_t HELPER(tcxb)(uint32_t f1, uint64_t m2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ CPU_QuadU v1;
|
|
|
5544c1 |
+ uint32_t cc = 0;
|
|
|
5544c1 |
+ int neg;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ v1.ll.upper = env->fregs[f1].ll;
|
|
|
5544c1 |
+ v1.ll.lower = env->fregs[f1 + 2].ll;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ neg = float128_is_neg(v1.q);
|
|
|
5544c1 |
+ if ((float128_is_zero(v1.q) && (m2 & (1 << (11-neg)))) ||
|
|
|
5544c1 |
+ (float128_is_infinity(v1.q) && (m2 & (1 << (5-neg)))) ||
|
|
|
5544c1 |
+ (float128_is_any_nan(v1.q) && (m2 & (1 << (3-neg)))) ||
|
|
|
5544c1 |
+ (float128_is_signaling_nan(v1.q) && (m2 & (1 << (1-neg))))) {
|
|
|
5544c1 |
+ cc = 1;
|
|
|
5544c1 |
+ } else if (m2 & (1 << (9-neg))) {
|
|
|
5544c1 |
+ /* assume normalized number */
|
|
|
5544c1 |
+ cc = 1;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+ /* FIXME: denormalized? */
|
|
|
5544c1 |
+ return cc;
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* square root 64-bit RR */
|
|
|
5544c1 |
+void HELPER(sqdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ env->fregs[f1].d = float64_sqrt(env->fregs[f2].d, &env->fpu_status);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
|
|
|
5544c1 |
index 195e93e..270bf14 100644
|
|
|
5544c1 |
--- a/target-s390x/op_helper.c
|
|
|
5544c1 |
+++ b/target-s390x/op_helper.c
|
|
|
5544c1 |
@@ -977,802 +977,6 @@ uint32_t HELPER(slbg)(uint32_t cc, uint32_t r1, uint64_t v1, uint64_t v2)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static inline int float_comp_to_cc(int float_compare)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- switch (float_compare) {
|
|
|
5544c1 |
- case float_relation_equal:
|
|
|
5544c1 |
- return 0;
|
|
|
5544c1 |
- case float_relation_less:
|
|
|
5544c1 |
- return 1;
|
|
|
5544c1 |
- case float_relation_greater:
|
|
|
5544c1 |
- return 2;
|
|
|
5544c1 |
- case float_relation_unordered:
|
|
|
5544c1 |
- return 3;
|
|
|
5544c1 |
- default:
|
|
|
5544c1 |
- cpu_abort(env, "unknown return value for float compare\n");
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* condition codes for binary FP ops */
|
|
|
5544c1 |
-static uint32_t set_cc_f32(float32 v1, float32 v2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- return float_comp_to_cc(float32_compare_quiet(v1, v2, &env->fpu_status));
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-static uint32_t set_cc_f64(float64 v1, float64 v2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- return float_comp_to_cc(float64_compare_quiet(v1, v2, &env->fpu_status));
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* condition codes for unary FP ops */
|
|
|
5544c1 |
-static uint32_t set_cc_nz_f32(float32 v)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- if (float32_is_any_nan(v)) {
|
|
|
5544c1 |
- return 3;
|
|
|
5544c1 |
- } else if (float32_is_zero(v)) {
|
|
|
5544c1 |
- return 0;
|
|
|
5544c1 |
- } else if (float32_is_neg(v)) {
|
|
|
5544c1 |
- return 1;
|
|
|
5544c1 |
- } else {
|
|
|
5544c1 |
- return 2;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-static uint32_t set_cc_nz_f64(float64 v)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- if (float64_is_any_nan(v)) {
|
|
|
5544c1 |
- return 3;
|
|
|
5544c1 |
- } else if (float64_is_zero(v)) {
|
|
|
5544c1 |
- return 0;
|
|
|
5544c1 |
- } else if (float64_is_neg(v)) {
|
|
|
5544c1 |
- return 1;
|
|
|
5544c1 |
- } else {
|
|
|
5544c1 |
- return 2;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-static uint32_t set_cc_nz_f128(float128 v)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- if (float128_is_any_nan(v)) {
|
|
|
5544c1 |
- return 3;
|
|
|
5544c1 |
- } else if (float128_is_zero(v)) {
|
|
|
5544c1 |
- return 0;
|
|
|
5544c1 |
- } else if (float128_is_neg(v)) {
|
|
|
5544c1 |
- return 1;
|
|
|
5544c1 |
- } else {
|
|
|
5544c1 |
- return 2;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 32-bit int to 64-bit float */
|
|
|
5544c1 |
-void HELPER(cdfbr)(uint32_t f1, int32_t v2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- HELPER_LOG("%s: converting %d to f%d\n", __func__, v2, f1);
|
|
|
5544c1 |
- env->fregs[f1].d = int32_to_float64(v2, &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 32-bit int to 128-bit float */
|
|
|
5544c1 |
-void HELPER(cxfbr)(uint32_t f1, int32_t v2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU v1;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v1.q = int32_to_float128(v2, &env->fpu_status);
|
|
|
5544c1 |
- env->fregs[f1].ll = v1.ll.upper;
|
|
|
5544c1 |
- env->fregs[f1 + 2].ll = v1.ll.lower;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 64-bit int to 32-bit float */
|
|
|
5544c1 |
-void HELPER(cegbr)(uint32_t f1, int64_t v2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
|
|
|
5544c1 |
- env->fregs[f1].l.upper = int64_to_float32(v2, &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 64-bit int to 64-bit float */
|
|
|
5544c1 |
-void HELPER(cdgbr)(uint32_t f1, int64_t v2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- HELPER_LOG("%s: converting %ld to f%d\n", __func__, v2, f1);
|
|
|
5544c1 |
- env->fregs[f1].d = int64_to_float64(v2, &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 64-bit int to 128-bit float */
|
|
|
5544c1 |
-void HELPER(cxgbr)(uint32_t f1, int64_t v2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU x1;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- x1.q = int64_to_float128(v2, &env->fpu_status);
|
|
|
5544c1 |
- HELPER_LOG("%s: converted %ld to 0x%lx and 0x%lx\n", __func__, v2,
|
|
|
5544c1 |
- x1.ll.upper, x1.ll.lower);
|
|
|
5544c1 |
- env->fregs[f1].ll = x1.ll.upper;
|
|
|
5544c1 |
- env->fregs[f1 + 2].ll = x1.ll.lower;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 32-bit int to 32-bit float */
|
|
|
5544c1 |
-void HELPER(cefbr)(uint32_t f1, int32_t v2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].l.upper = int32_to_float32(v2, &env->fpu_status);
|
|
|
5544c1 |
- HELPER_LOG("%s: converting %d to 0x%d in f%d\n", __func__, v2,
|
|
|
5544c1 |
- env->fregs[f1].l.upper, f1);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 32-bit FP addition RR */
|
|
|
5544c1 |
-uint32_t HELPER(aebr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
|
|
|
5544c1 |
- env->fregs[f2].l.upper,
|
|
|
5544c1 |
- &env->fpu_status);
|
|
|
5544c1 |
- HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
|
|
|
5544c1 |
- env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return set_cc_nz_f32(env->fregs[f1].l.upper);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 64-bit FP addition RR */
|
|
|
5544c1 |
-uint32_t HELPER(adbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].d = float64_add(env->fregs[f1].d, env->fregs[f2].d,
|
|
|
5544c1 |
- &env->fpu_status);
|
|
|
5544c1 |
- HELPER_LOG("%s: adding 0x%ld resulting in 0x%ld in f%d\n", __func__,
|
|
|
5544c1 |
- env->fregs[f2].d, env->fregs[f1].d, f1);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return set_cc_nz_f64(env->fregs[f1].d);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 32-bit FP subtraction RR */
|
|
|
5544c1 |
-uint32_t HELPER(sebr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].l.upper = float32_sub(env->fregs[f1].l.upper,
|
|
|
5544c1 |
- env->fregs[f2].l.upper,
|
|
|
5544c1 |
- &env->fpu_status);
|
|
|
5544c1 |
- HELPER_LOG("%s: adding 0x%d resulting in 0x%d in f%d\n", __func__,
|
|
|
5544c1 |
- env->fregs[f2].l.upper, env->fregs[f1].l.upper, f1);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return set_cc_nz_f32(env->fregs[f1].l.upper);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 64-bit FP subtraction RR */
|
|
|
5544c1 |
-uint32_t HELPER(sdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].d = float64_sub(env->fregs[f1].d, env->fregs[f2].d,
|
|
|
5544c1 |
- &env->fpu_status);
|
|
|
5544c1 |
- HELPER_LOG("%s: subtracting 0x%ld resulting in 0x%ld in f%d\n",
|
|
|
5544c1 |
- __func__, env->fregs[f2].d, env->fregs[f1].d, f1);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return set_cc_nz_f64(env->fregs[f1].d);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 32-bit FP division RR */
|
|
|
5544c1 |
-void HELPER(debr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].l.upper = float32_div(env->fregs[f1].l.upper,
|
|
|
5544c1 |
- env->fregs[f2].l.upper,
|
|
|
5544c1 |
- &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 128-bit FP division RR */
|
|
|
5544c1 |
-void HELPER(dxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU v1;
|
|
|
5544c1 |
- CPU_QuadU v2;
|
|
|
5544c1 |
- CPU_QuadU res;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v1.ll.upper = env->fregs[f1].ll;
|
|
|
5544c1 |
- v1.ll.lower = env->fregs[f1 + 2].ll;
|
|
|
5544c1 |
- v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
- v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
- res.q = float128_div(v1.q, v2.q, &env->fpu_status);
|
|
|
5544c1 |
- env->fregs[f1].ll = res.ll.upper;
|
|
|
5544c1 |
- env->fregs[f1 + 2].ll = res.ll.lower;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 64-bit FP multiplication RR */
|
|
|
5544c1 |
-void HELPER(mdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].d = float64_mul(env->fregs[f1].d, env->fregs[f2].d,
|
|
|
5544c1 |
- &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 128-bit FP multiplication RR */
|
|
|
5544c1 |
-void HELPER(mxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU v1;
|
|
|
5544c1 |
- CPU_QuadU v2;
|
|
|
5544c1 |
- CPU_QuadU res;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v1.ll.upper = env->fregs[f1].ll;
|
|
|
5544c1 |
- v1.ll.lower = env->fregs[f1 + 2].ll;
|
|
|
5544c1 |
- v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
- v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
- res.q = float128_mul(v1.q, v2.q, &env->fpu_status);
|
|
|
5544c1 |
- env->fregs[f1].ll = res.ll.upper;
|
|
|
5544c1 |
- env->fregs[f1 + 2].ll = res.ll.lower;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 32-bit float to 64-bit float */
|
|
|
5544c1 |
-void HELPER(ldebr)(uint32_t r1, uint32_t r2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[r1].d = float32_to_float64(env->fregs[r2].l.upper,
|
|
|
5544c1 |
- &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 128-bit float to 64-bit float */
|
|
|
5544c1 |
-void HELPER(ldxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU x2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- x2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
- x2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
- env->fregs[f1].d = float128_to_float64(x2.q, &env->fpu_status);
|
|
|
5544c1 |
- HELPER_LOG("%s: to 0x%ld\n", __func__, env->fregs[f1].d);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 64-bit float to 128-bit float */
|
|
|
5544c1 |
-void HELPER(lxdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU res;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- res.q = float64_to_float128(env->fregs[f2].d, &env->fpu_status);
|
|
|
5544c1 |
- env->fregs[f1].ll = res.ll.upper;
|
|
|
5544c1 |
- env->fregs[f1 + 2].ll = res.ll.lower;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 64-bit float to 32-bit float */
|
|
|
5544c1 |
-void HELPER(ledbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float64 d2 = env->fregs[f2].d;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- env->fregs[f1].l.upper = float64_to_float32(d2, &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 128-bit float to 32-bit float */
|
|
|
5544c1 |
-void HELPER(lexbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU x2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- x2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
- x2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
- env->fregs[f1].l.upper = float128_to_float32(x2.q, &env->fpu_status);
|
|
|
5544c1 |
- HELPER_LOG("%s: to 0x%d\n", __func__, env->fregs[f1].l.upper);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* absolute value of 32-bit float */
|
|
|
5544c1 |
-uint32_t HELPER(lpebr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float32 v1;
|
|
|
5544c1 |
- float32 v2 = env->fregs[f2].d;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v1 = float32_abs(v2);
|
|
|
5544c1 |
- env->fregs[f1].d = v1;
|
|
|
5544c1 |
- return set_cc_nz_f32(v1);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* absolute value of 64-bit float */
|
|
|
5544c1 |
-uint32_t HELPER(lpdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float64 v1;
|
|
|
5544c1 |
- float64 v2 = env->fregs[f2].d;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v1 = float64_abs(v2);
|
|
|
5544c1 |
- env->fregs[f1].d = v1;
|
|
|
5544c1 |
- return set_cc_nz_f64(v1);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* absolute value of 128-bit float */
|
|
|
5544c1 |
-uint32_t HELPER(lpxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU v1;
|
|
|
5544c1 |
- CPU_QuadU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
- v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
- v1.q = float128_abs(v2.q);
|
|
|
5544c1 |
- env->fregs[f1].ll = v1.ll.upper;
|
|
|
5544c1 |
- env->fregs[f1 + 2].ll = v1.ll.lower;
|
|
|
5544c1 |
- return set_cc_nz_f128(v1.q);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* load and test 64-bit float */
|
|
|
5544c1 |
-uint32_t HELPER(ltdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].d = env->fregs[f2].d;
|
|
|
5544c1 |
- return set_cc_nz_f64(env->fregs[f1].d);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* load and test 32-bit float */
|
|
|
5544c1 |
-uint32_t HELPER(ltebr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].l.upper = env->fregs[f2].l.upper;
|
|
|
5544c1 |
- return set_cc_nz_f32(env->fregs[f1].l.upper);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* load and test 128-bit float */
|
|
|
5544c1 |
-uint32_t HELPER(ltxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU x;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- x.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
- x.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
- env->fregs[f1].ll = x.ll.upper;
|
|
|
5544c1 |
- env->fregs[f1 + 2].ll = x.ll.lower;
|
|
|
5544c1 |
- return set_cc_nz_f128(x.q);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* load complement of 32-bit float */
|
|
|
5544c1 |
-uint32_t HELPER(lcebr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].l.upper = float32_chs(env->fregs[f2].l.upper);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return set_cc_nz_f32(env->fregs[f1].l.upper);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* load complement of 64-bit float */
|
|
|
5544c1 |
-uint32_t HELPER(lcdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].d = float64_chs(env->fregs[f2].d);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return set_cc_nz_f64(env->fregs[f1].d);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* load complement of 128-bit float */
|
|
|
5544c1 |
-uint32_t HELPER(lcxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU x1, x2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- x2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
- x2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
- x1.q = float128_chs(x2.q);
|
|
|
5544c1 |
- env->fregs[f1].ll = x1.ll.upper;
|
|
|
5544c1 |
- env->fregs[f1 + 2].ll = x1.ll.lower;
|
|
|
5544c1 |
- return set_cc_nz_f128(x1.q);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 32-bit FP addition RM */
|
|
|
5544c1 |
-void HELPER(aeb)(uint32_t f1, uint32_t val)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float32 v1 = env->fregs[f1].l.upper;
|
|
|
5544c1 |
- CPU_FloatU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2.l = val;
|
|
|
5544c1 |
- HELPER_LOG("%s: adding 0x%d from f%d and 0x%d\n", __func__,
|
|
|
5544c1 |
- v1, f1, v2.f);
|
|
|
5544c1 |
- env->fregs[f1].l.upper = float32_add(v1, v2.f, &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 32-bit FP division RM */
|
|
|
5544c1 |
-void HELPER(deb)(uint32_t f1, uint32_t val)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float32 v1 = env->fregs[f1].l.upper;
|
|
|
5544c1 |
- CPU_FloatU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2.l = val;
|
|
|
5544c1 |
- HELPER_LOG("%s: dividing 0x%d from f%d by 0x%d\n", __func__,
|
|
|
5544c1 |
- v1, f1, v2.f);
|
|
|
5544c1 |
- env->fregs[f1].l.upper = float32_div(v1, v2.f, &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 32-bit FP multiplication RM */
|
|
|
5544c1 |
-void HELPER(meeb)(uint32_t f1, uint32_t val)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float32 v1 = env->fregs[f1].l.upper;
|
|
|
5544c1 |
- CPU_FloatU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2.l = val;
|
|
|
5544c1 |
- HELPER_LOG("%s: multiplying 0x%d from f%d and 0x%d\n", __func__,
|
|
|
5544c1 |
- v1, f1, v2.f);
|
|
|
5544c1 |
- env->fregs[f1].l.upper = float32_mul(v1, v2.f, &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 32-bit FP compare RR */
|
|
|
5544c1 |
-uint32_t HELPER(cebr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float32 v1 = env->fregs[f1].l.upper;
|
|
|
5544c1 |
- float32 v2 = env->fregs[f2].l.upper;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- HELPER_LOG("%s: comparing 0x%d from f%d and 0x%d\n", __func__,
|
|
|
5544c1 |
- v1, f1, v2);
|
|
|
5544c1 |
- return set_cc_f32(v1, v2);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 64-bit FP compare RR */
|
|
|
5544c1 |
-uint32_t HELPER(cdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
- float64 v2 = env->fregs[f2].d;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%ld\n", __func__,
|
|
|
5544c1 |
- v1, f1, v2);
|
|
|
5544c1 |
- return set_cc_f64(v1, v2);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 128-bit FP compare RR */
|
|
|
5544c1 |
-uint32_t HELPER(cxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU v1;
|
|
|
5544c1 |
- CPU_QuadU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v1.ll.upper = env->fregs[f1].ll;
|
|
|
5544c1 |
- v1.ll.lower = env->fregs[f1 + 2].ll;
|
|
|
5544c1 |
- v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
- v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return float_comp_to_cc(float128_compare_quiet(v1.q, v2.q,
|
|
|
5544c1 |
- &env->fpu_status));
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 64-bit FP compare RM */
|
|
|
5544c1 |
-uint32_t HELPER(cdb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
- CPU_DoubleU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2.ll = ldq(a2);
|
|
|
5544c1 |
- HELPER_LOG("%s: comparing 0x%ld from f%d and 0x%lx\n", __func__, v1,
|
|
|
5544c1 |
- f1, v2.d);
|
|
|
5544c1 |
- return set_cc_f64(v1, v2.d);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 64-bit FP addition RM */
|
|
|
5544c1 |
-uint32_t HELPER(adb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
- CPU_DoubleU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2.ll = ldq(a2);
|
|
|
5544c1 |
- HELPER_LOG("%s: adding 0x%lx from f%d and 0x%lx\n", __func__,
|
|
|
5544c1 |
- v1, f1, v2.d);
|
|
|
5544c1 |
- env->fregs[f1].d = v1 = float64_add(v1, v2.d, &env->fpu_status);
|
|
|
5544c1 |
- return set_cc_nz_f64(v1);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 32-bit FP subtraction RM */
|
|
|
5544c1 |
-void HELPER(seb)(uint32_t f1, uint32_t val)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float32 v1 = env->fregs[f1].l.upper;
|
|
|
5544c1 |
- CPU_FloatU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2.l = val;
|
|
|
5544c1 |
- env->fregs[f1].l.upper = float32_sub(v1, v2.f, &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 64-bit FP subtraction RM */
|
|
|
5544c1 |
-uint32_t HELPER(sdb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
- CPU_DoubleU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2.ll = ldq(a2);
|
|
|
5544c1 |
- env->fregs[f1].d = v1 = float64_sub(v1, v2.d, &env->fpu_status);
|
|
|
5544c1 |
- return set_cc_nz_f64(v1);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 64-bit FP multiplication RM */
|
|
|
5544c1 |
-void HELPER(mdb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
- CPU_DoubleU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2.ll = ldq(a2);
|
|
|
5544c1 |
- HELPER_LOG("%s: multiplying 0x%lx from f%d and 0x%ld\n", __func__,
|
|
|
5544c1 |
- v1, f1, v2.d);
|
|
|
5544c1 |
- env->fregs[f1].d = float64_mul(v1, v2.d, &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 64-bit FP division RM */
|
|
|
5544c1 |
-void HELPER(ddb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
- CPU_DoubleU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2.ll = ldq(a2);
|
|
|
5544c1 |
- HELPER_LOG("%s: dividing 0x%lx from f%d by 0x%ld\n", __func__,
|
|
|
5544c1 |
- v1, f1, v2.d);
|
|
|
5544c1 |
- env->fregs[f1].d = float64_div(v1, v2.d, &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-static void set_round_mode(int m3)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- switch (m3) {
|
|
|
5544c1 |
- case 0:
|
|
|
5544c1 |
- /* current mode */
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- case 1:
|
|
|
5544c1 |
- /* biased round no nearest */
|
|
|
5544c1 |
- case 4:
|
|
|
5544c1 |
- /* round to nearest */
|
|
|
5544c1 |
- set_float_rounding_mode(float_round_nearest_even, &env->fpu_status);
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- case 5:
|
|
|
5544c1 |
- /* round to zero */
|
|
|
5544c1 |
- set_float_rounding_mode(float_round_to_zero, &env->fpu_status);
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- case 6:
|
|
|
5544c1 |
- /* round to +inf */
|
|
|
5544c1 |
- set_float_rounding_mode(float_round_up, &env->fpu_status);
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- case 7:
|
|
|
5544c1 |
- /* round to -inf */
|
|
|
5544c1 |
- set_float_rounding_mode(float_round_down, &env->fpu_status);
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 32-bit float to 64-bit int */
|
|
|
5544c1 |
-uint32_t HELPER(cgebr)(uint32_t r1, uint32_t f2, uint32_t m3)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float32 v2 = env->fregs[f2].l.upper;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- set_round_mode(m3);
|
|
|
5544c1 |
- env->regs[r1] = float32_to_int64(v2, &env->fpu_status);
|
|
|
5544c1 |
- return set_cc_nz_f32(v2);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 64-bit float to 64-bit int */
|
|
|
5544c1 |
-uint32_t HELPER(cgdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float64 v2 = env->fregs[f2].d;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- set_round_mode(m3);
|
|
|
5544c1 |
- env->regs[r1] = float64_to_int64(v2, &env->fpu_status);
|
|
|
5544c1 |
- return set_cc_nz_f64(v2);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 128-bit float to 64-bit int */
|
|
|
5544c1 |
-uint32_t HELPER(cgxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
- v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
- set_round_mode(m3);
|
|
|
5544c1 |
- env->regs[r1] = float128_to_int64(v2.q, &env->fpu_status);
|
|
|
5544c1 |
- if (float128_is_any_nan(v2.q)) {
|
|
|
5544c1 |
- return 3;
|
|
|
5544c1 |
- } else if (float128_is_zero(v2.q)) {
|
|
|
5544c1 |
- return 0;
|
|
|
5544c1 |
- } else if (float128_is_neg(v2.q)) {
|
|
|
5544c1 |
- return 1;
|
|
|
5544c1 |
- } else {
|
|
|
5544c1 |
- return 2;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 32-bit float to 32-bit int */
|
|
|
5544c1 |
-uint32_t HELPER(cfebr)(uint32_t r1, uint32_t f2, uint32_t m3)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float32 v2 = env->fregs[f2].l.upper;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- set_round_mode(m3);
|
|
|
5544c1 |
- env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
|
|
|
5544c1 |
- float32_to_int32(v2, &env->fpu_status);
|
|
|
5544c1 |
- return set_cc_nz_f32(v2);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 64-bit float to 32-bit int */
|
|
|
5544c1 |
-uint32_t HELPER(cfdbr)(uint32_t r1, uint32_t f2, uint32_t m3)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float64 v2 = env->fregs[f2].d;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- set_round_mode(m3);
|
|
|
5544c1 |
- env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
|
|
|
5544c1 |
- float64_to_int32(v2, &env->fpu_status);
|
|
|
5544c1 |
- return set_cc_nz_f64(v2);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 128-bit float to 32-bit int */
|
|
|
5544c1 |
-uint32_t HELPER(cfxbr)(uint32_t r1, uint32_t f2, uint32_t m3)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
- v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
- env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) |
|
|
|
5544c1 |
- float128_to_int32(v2.q, &env->fpu_status);
|
|
|
5544c1 |
- return set_cc_nz_f128(v2.q);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* load 32-bit FP zero */
|
|
|
5544c1 |
-void HELPER(lzer)(uint32_t f1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].l.upper = float32_zero;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* load 64-bit FP zero */
|
|
|
5544c1 |
-void HELPER(lzdr)(uint32_t f1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].d = float64_zero;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* load 128-bit FP zero */
|
|
|
5544c1 |
-void HELPER(lzxr)(uint32_t f1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU x;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- x.q = float64_to_float128(float64_zero, &env->fpu_status);
|
|
|
5544c1 |
- env->fregs[f1].ll = x.ll.upper;
|
|
|
5544c1 |
- env->fregs[f1 + 1].ll = x.ll.lower;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 128-bit FP subtraction RR */
|
|
|
5544c1 |
-uint32_t HELPER(sxbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU v1;
|
|
|
5544c1 |
- CPU_QuadU v2;
|
|
|
5544c1 |
- CPU_QuadU res;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v1.ll.upper = env->fregs[f1].ll;
|
|
|
5544c1 |
- v1.ll.lower = env->fregs[f1 + 2].ll;
|
|
|
5544c1 |
- v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
- v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
- res.q = float128_sub(v1.q, v2.q, &env->fpu_status);
|
|
|
5544c1 |
- env->fregs[f1].ll = res.ll.upper;
|
|
|
5544c1 |
- env->fregs[f1 + 2].ll = res.ll.lower;
|
|
|
5544c1 |
- return set_cc_nz_f128(res.q);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 128-bit FP addition RR */
|
|
|
5544c1 |
-uint32_t HELPER(axbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU v1;
|
|
|
5544c1 |
- CPU_QuadU v2;
|
|
|
5544c1 |
- CPU_QuadU res;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v1.ll.upper = env->fregs[f1].ll;
|
|
|
5544c1 |
- v1.ll.lower = env->fregs[f1 + 2].ll;
|
|
|
5544c1 |
- v2.ll.upper = env->fregs[f2].ll;
|
|
|
5544c1 |
- v2.ll.lower = env->fregs[f2 + 2].ll;
|
|
|
5544c1 |
- res.q = float128_add(v1.q, v2.q, &env->fpu_status);
|
|
|
5544c1 |
- env->fregs[f1].ll = res.ll.upper;
|
|
|
5544c1 |
- env->fregs[f1 + 2].ll = res.ll.lower;
|
|
|
5544c1 |
- return set_cc_nz_f128(res.q);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 32-bit FP multiplication RR */
|
|
|
5544c1 |
-void HELPER(meebr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].l.upper = float32_mul(env->fregs[f1].l.upper,
|
|
|
5544c1 |
- env->fregs[f2].l.upper,
|
|
|
5544c1 |
- &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 64-bit FP division RR */
|
|
|
5544c1 |
-void HELPER(ddbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].d = float64_div(env->fregs[f1].d, env->fregs[f2].d,
|
|
|
5544c1 |
- &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 64-bit FP multiply and add RM */
|
|
|
5544c1 |
-void HELPER(madb)(uint32_t f1, uint64_t a2, uint32_t f3)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_DoubleU v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- HELPER_LOG("%s: f1 %d a2 0x%lx f3 %d\n", __func__, f1, a2, f3);
|
|
|
5544c1 |
- v2.ll = ldq(a2);
|
|
|
5544c1 |
- env->fregs[f1].d = float64_add(env->fregs[f1].d,
|
|
|
5544c1 |
- float64_mul(v2.d, env->fregs[f3].d,
|
|
|
5544c1 |
- &env->fpu_status),
|
|
|
5544c1 |
- &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 64-bit FP multiply and add RR */
|
|
|
5544c1 |
-void HELPER(madbr)(uint32_t f1, uint32_t f3, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
|
|
|
5544c1 |
- env->fregs[f1].d = float64_add(float64_mul(env->fregs[f2].d,
|
|
|
5544c1 |
- env->fregs[f3].d,
|
|
|
5544c1 |
- &env->fpu_status),
|
|
|
5544c1 |
- env->fregs[f1].d, &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 64-bit FP multiply and subtract RR */
|
|
|
5544c1 |
-void HELPER(msdbr)(uint32_t f1, uint32_t f3, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- HELPER_LOG("%s: f1 %d f2 %d f3 %d\n", __func__, f1, f2, f3);
|
|
|
5544c1 |
- env->fregs[f1].d = float64_sub(float64_mul(env->fregs[f2].d,
|
|
|
5544c1 |
- env->fregs[f3].d,
|
|
|
5544c1 |
- &env->fpu_status),
|
|
|
5544c1 |
- env->fregs[f1].d, &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* 32-bit FP multiply and add RR */
|
|
|
5544c1 |
-void HELPER(maebr)(uint32_t f1, uint32_t f3, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].l.upper = float32_add(env->fregs[f1].l.upper,
|
|
|
5544c1 |
- float32_mul(env->fregs[f2].l.upper,
|
|
|
5544c1 |
- env->fregs[f3].l.upper,
|
|
|
5544c1 |
- &env->fpu_status),
|
|
|
5544c1 |
- &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 32-bit float to 64-bit float */
|
|
|
5544c1 |
-void HELPER(ldeb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- uint32_t v2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2 = ldl(a2);
|
|
|
5544c1 |
- env->fregs[f1].d = float32_to_float64(v2,
|
|
|
5544c1 |
- &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* convert 64-bit float to 128-bit float */
|
|
|
5544c1 |
-void HELPER(lxdb)(uint32_t f1, uint64_t a2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_DoubleU v2;
|
|
|
5544c1 |
- CPU_QuadU v1;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v2.ll = ldq(a2);
|
|
|
5544c1 |
- v1.q = float64_to_float128(v2.d, &env->fpu_status);
|
|
|
5544c1 |
- env->fregs[f1].ll = v1.ll.upper;
|
|
|
5544c1 |
- env->fregs[f1 + 2].ll = v1.ll.lower;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* test data class 32-bit */
|
|
|
5544c1 |
-uint32_t HELPER(tceb)(uint32_t f1, uint64_t m2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float32 v1 = env->fregs[f1].l.upper;
|
|
|
5544c1 |
- int neg = float32_is_neg(v1);
|
|
|
5544c1 |
- uint32_t cc = 0;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, (long)v1, m2, neg);
|
|
|
5544c1 |
- if ((float32_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
|
|
|
5544c1 |
- (float32_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
|
|
|
5544c1 |
- (float32_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
|
|
|
5544c1 |
- (float32_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
|
|
|
5544c1 |
- cc = 1;
|
|
|
5544c1 |
- } else if (m2 & (1 << (9-neg))) {
|
|
|
5544c1 |
- /* assume normalized number */
|
|
|
5544c1 |
- cc = 1;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- /* FIXME: denormalized? */
|
|
|
5544c1 |
- return cc;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* test data class 64-bit */
|
|
|
5544c1 |
-uint32_t HELPER(tcdb)(uint32_t f1, uint64_t m2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- float64 v1 = env->fregs[f1].d;
|
|
|
5544c1 |
- int neg = float64_is_neg(v1);
|
|
|
5544c1 |
- uint32_t cc = 0;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- HELPER_LOG("%s: v1 0x%lx m2 0x%lx neg %d\n", __func__, v1, m2, neg);
|
|
|
5544c1 |
- if ((float64_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
|
|
|
5544c1 |
- (float64_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
|
|
|
5544c1 |
- (float64_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
|
|
|
5544c1 |
- (float64_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
|
|
|
5544c1 |
- cc = 1;
|
|
|
5544c1 |
- } else if (m2 & (1 << (9-neg))) {
|
|
|
5544c1 |
- /* assume normalized number */
|
|
|
5544c1 |
- cc = 1;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
- /* FIXME: denormalized? */
|
|
|
5544c1 |
- return cc;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* test data class 128-bit */
|
|
|
5544c1 |
-uint32_t HELPER(tcxb)(uint32_t f1, uint64_t m2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- CPU_QuadU v1;
|
|
|
5544c1 |
- uint32_t cc = 0;
|
|
|
5544c1 |
- int neg;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- v1.ll.upper = env->fregs[f1].ll;
|
|
|
5544c1 |
- v1.ll.lower = env->fregs[f1 + 2].ll;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- neg = float128_is_neg(v1.q);
|
|
|
5544c1 |
- if ((float128_is_zero(v1.q) && (m2 & (1 << (11-neg)))) ||
|
|
|
5544c1 |
- (float128_is_infinity(v1.q) && (m2 & (1 << (5-neg)))) ||
|
|
|
5544c1 |
- (float128_is_any_nan(v1.q) && (m2 & (1 << (3-neg)))) ||
|
|
|
5544c1 |
- (float128_is_signaling_nan(v1.q) && (m2 & (1 << (1-neg))))) {
|
|
|
5544c1 |
- cc = 1;
|
|
|
5544c1 |
- } else if (m2 & (1 << (9-neg))) {
|
|
|
5544c1 |
- /* assume normalized number */
|
|
|
5544c1 |
- cc = 1;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
- /* FIXME: denormalized? */
|
|
|
5544c1 |
- return cc;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
/* find leftmost one */
|
|
|
5544c1 |
uint32_t HELPER(flogr)(uint32_t r1, uint64_t v2)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
@@ -1795,12 +999,6 @@ uint32_t HELPER(flogr)(uint32_t r1, uint64_t v2)
|
|
|
5544c1 |
}
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-/* square root 64-bit RR */
|
|
|
5544c1 |
-void HELPER(sqdbr)(uint32_t f1, uint32_t f2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- env->fregs[f1].d = float64_sqrt(env->fregs[f2].d, &env->fpu_status);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
/* checksum */
|
|
|
5544c1 |
void HELPER(cksm)(uint32_t r1, uint32_t r2)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
|
|
|
5544c1 |
index 1c1baf5..c370df3 100644
|
|
|
5544c1 |
--- a/target-s390x/translate.c
|
|
|
5544c1 |
+++ b/target-s390x/translate.c
|
|
|
5544c1 |
@@ -667,16 +667,11 @@ static void set_cc_cmp_f32_i64(DisasContext *s, TCGv_i32 v1, TCGv_i64 v2)
|
|
|
5544c1 |
s->cc_op = CC_OP_LTGT_F32;
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static void set_cc_nz_f32(DisasContext *s, TCGv_i32 v1)
|
|
|
5544c1 |
+static void gen_set_cc_nz_f32(DisasContext *s, TCGv_i32 v1)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
gen_op_update1_cc_i32(s, CC_OP_NZ_F32, v1);
|
|
|
5544c1 |
}
|
|
|
5544c1 |
|
|
|
5544c1 |
-static inline void set_cc_nz_f64(DisasContext *s, TCGv_i64 v1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- gen_op_update1_cc_i64(s, CC_OP_NZ_F64, v1);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
/* CC value is in env->cc_op */
|
|
|
5544c1 |
static inline void set_cc_static(DisasContext *s)
|
|
|
5544c1 |
{
|
|
|
5544c1 |
@@ -2235,7 +2230,7 @@ static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,
|
|
|
5544c1 |
tcg_temp_free_i32(tmp32);
|
|
|
5544c1 |
|
|
|
5544c1 |
tmp32 = load_freg32(r1);
|
|
|
5544c1 |
- set_cc_nz_f32(s, tmp32);
|
|
|
5544c1 |
+ gen_set_cc_nz_f32(s, tmp32);
|
|
|
5544c1 |
tcg_temp_free_i32(tmp32);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case 0xb: /* SEB R1,D2(X2,B2) [RXE] */
|
|
|
5544c1 |
@@ -2248,7 +2243,7 @@ static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,
|
|
|
5544c1 |
tcg_temp_free_i32(tmp32);
|
|
|
5544c1 |
|
|
|
5544c1 |
tmp32 = load_freg32(r1);
|
|
|
5544c1 |
- set_cc_nz_f32(s, tmp32);
|
|
|
5544c1 |
+ gen_set_cc_nz_f32(s, tmp32);
|
|
|
5544c1 |
tcg_temp_free_i32(tmp32);
|
|
|
5544c1 |
break;
|
|
|
5544c1 |
case 0xd: /* DEB R1,D2(X2,B2) [RXE] */
|
|
|
5544c1 |
--
|
|
|
5544c1 |
1.7.12.1
|
|
|
5544c1 |
|