From 727ebf3f24a6f519aab1306bad6e63014c76aec5 Mon Sep 17 00:00:00 2001 From: Fam Zheng Date: Fri, 19 May 2017 00:35:18 +0200 Subject: [PATCH 13/18] serial: update LSR on enabling/disabling FIFOs RH-Author: Fam Zheng Message-id: <20170519003523.21163-14-famz@redhat.com> Patchwork-id: 75369 O-Subject: [RHEL-7.3.z qemu-kvm PATCH 13/18] serial: update LSR on enabling/disabling FIFOs Bugzilla: 1452332 RH-Acked-by: Paolo Bonzini RH-Acked-by: Laurent Vivier RH-Acked-by: Eduardo Habkost From: Paolo Bonzini When the transmit FIFO is emptied or enabled, the transmitter hold register is empty. When it is disabled, it is also emptied and in addition the previous contents of the transmitter hold register are discarded. In either case, the THRE bit in LSR must be set and THRI raised. When the receive FIFO is emptied or enabled, the data ready and break bits must be cleared in LSR. Likewise when the receive FIFO is disabled. Reviewed-by: Dr. David Alan Gilbert Signed-off-by: Paolo Bonzini (cherry picked from commit 023c3a9707d0d9259a1e858cdf7804dd10973fca) Signed-off-by: Fam Zheng Signed-off-by: Miroslav Rezanina Conflicts: hw/char/serial.c Contextual conflict because upstream uses new timer API timer_del while downstream still uses qemu_del_timer. --- hw/char/serial.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/char/serial.c b/hw/char/serial.c index c2be4bd..e0d29a8 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -351,12 +351,15 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, /* FIFO clear */ if (val & UART_FCR_RFR) { + s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); qemu_del_timer(s->fifo_timeout_timer); s->timeout_ipending=0; fifo8_reset(&s->recv_fifo); } if (val & UART_FCR_XFR) { + s->lsr |= UART_LSR_THRE; + s->thr_ipending = 1; fifo8_reset(&s->xmit_fifo); } -- 1.8.3.1