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From 5d8e4aefe49d4ea5237efc8132e44183b99ebabc Mon Sep 17 00:00:00 2001
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From: Vitaly Kuznetsov <vkuznets@redhat.com>
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Date: Wed, 16 Mar 2022 09:35:23 +0100
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Subject: [PATCH 03/14] vmxcap: Add 5-level EPT bit
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RH-Author: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-MergeRequest: 126: i386: Add Icelake-Server-v6 CPU model with 5-level EPT support
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RH-Commit: [1/2] 3f74e192278b8886de5dbeaf607521e9d3b744eb
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RH-Bugzilla: 2038051
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Cornelia Huck <cohuck@redhat.com>
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2038051
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Brew: https://brewweb.engineering.redhat.com/brew/taskinfo?taskID=43862630
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commit d312378e59658473aa91aa15c67ec6200d92e5ff
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Author: Vitaly Kuznetsov <vkuznets@redhat.com>
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Date: Mon Feb 21 15:53:16 2022 +0100
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vmxcap: Add 5-level EPT bit
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5-level EPT is present in Icelake Server CPUs and is supported by QEMU
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('vmx-page-walk-5').
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Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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Message-Id: <20220221145316.576138-2-vkuznets@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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---
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scripts/kvm/vmxcap | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/scripts/kvm/vmxcap b/scripts/kvm/vmxcap
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index 6fe66d5f57..f140040104 100755
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--- a/scripts/kvm/vmxcap
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+++ b/scripts/kvm/vmxcap
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@@ -249,6 +249,7 @@ controls = [
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bits = {
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0: 'Execute-only EPT translations',
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6: 'Page-walk length 4',
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+ 7: 'Page-walk length 5',
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8: 'Paging-structure memory type UC',
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14: 'Paging-structure memory type WB',
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16: '2MB EPT pages',
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--
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2.31.1
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