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From d7852bf27b3c4bb0fa932d171325c3d386550ebe Mon Sep 17 00:00:00 2001
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From: Gerd Hoffmann <kraxel@redhat.com>
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Date: Fri, 11 Jul 2014 14:20:35 +0200
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Subject: [PATCH 02/43] usb/hcd-xhci: QOM parent field cleanup
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Message-id: <1405088470-24115-3-git-send-email-kraxel@redhat.com>
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Patchwork-id: 59826
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O-Subject: [RHEL-7.1 qemu-kvm PATCH 02/37] usb/hcd-xhci: QOM parent field cleanup
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Bugzilla: 980747
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RH-Acked-by: Dr. David Alan Gilbert (git) <dgilbert@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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From: Andreas Färber <afaerber@suse.de>
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Replace direct uses of XHCIState::pci_dev with QOM casts and rename it
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to parent_obj.
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Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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Signed-off-by: Andreas Färber <afaerber@suse.de>
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(cherry picked from commit 9b7d3334d062e8c9e4f1b0ad3df35abb08cd8bf0)
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---
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hw/usb/hcd-xhci.c | 83 ++++++++++++++++++++++++++++++++-----------------------
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1 file changed, 48 insertions(+), 35 deletions(-)
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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hw/usb/hcd-xhci.c | 83 ++++++++++++++++++++++++++++++++-----------------------
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1 file changed, 48 insertions(+), 35 deletions(-)
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diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
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index 8fa1c6e..724c412 100644
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--- a/hw/usb/hcd-xhci.c
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+++ b/hw/usb/hcd-xhci.c
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@@ -446,7 +446,10 @@ typedef struct XHCIInterrupter {
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} XHCIInterrupter;
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struct XHCIState {
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- PCIDevice pci_dev;
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+ /*< private >*/
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+ PCIDevice parent_obj;
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+ /*< public >*/
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+
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USBBus bus;
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qemu_irq irq;
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MemoryRegion mem;
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@@ -662,7 +665,7 @@ static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
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assert((len % sizeof(uint32_t)) == 0);
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- pci_dma_read(&xhci->pci_dev, addr, buf, len);
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+ pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
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for (i = 0; i < (len / sizeof(uint32_t)); i++) {
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buf[i] = le32_to_cpu(buf[i]);
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@@ -680,7 +683,7 @@ static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
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for (i = 0; i < (len / sizeof(uint32_t)); i++) {
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tmp[i] = cpu_to_le32(buf[i]);
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}
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- pci_dma_write(&xhci->pci_dev, addr, tmp, len);
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+ pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
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}
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static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
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@@ -707,10 +710,11 @@ static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
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static void xhci_intx_update(XHCIState *xhci)
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{
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+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
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int level = 0;
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- if (msix_enabled(&xhci->pci_dev) ||
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- msi_enabled(&xhci->pci_dev)) {
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+ if (msix_enabled(pci_dev) ||
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+ msi_enabled(pci_dev)) {
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return;
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}
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@@ -726,9 +730,10 @@ static void xhci_intx_update(XHCIState *xhci)
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static void xhci_msix_update(XHCIState *xhci, int v)
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{
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+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
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bool enabled;
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- if (!msix_enabled(&xhci->pci_dev)) {
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+ if (!msix_enabled(pci_dev)) {
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return;
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}
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@@ -739,17 +744,19 @@ static void xhci_msix_update(XHCIState *xhci, int v)
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if (enabled) {
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trace_usb_xhci_irq_msix_use(v);
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- msix_vector_use(&xhci->pci_dev, v);
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+ msix_vector_use(pci_dev, v);
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xhci->intr[v].msix_used = true;
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} else {
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trace_usb_xhci_irq_msix_unuse(v);
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- msix_vector_unuse(&xhci->pci_dev, v);
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+ msix_vector_unuse(pci_dev, v);
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xhci->intr[v].msix_used = false;
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}
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}
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static void xhci_intr_raise(XHCIState *xhci, int v)
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{
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+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
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+
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xhci->intr[v].erdp_low |= ERDP_EHB;
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xhci->intr[v].iman |= IMAN_IP;
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xhci->usbsts |= USBSTS_EINT;
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@@ -762,15 +769,15 @@ static void xhci_intr_raise(XHCIState *xhci, int v)
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return;
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}
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- if (msix_enabled(&xhci->pci_dev)) {
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+ if (msix_enabled(pci_dev)) {
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trace_usb_xhci_irq_msix(v);
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- msix_notify(&xhci->pci_dev, v);
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+ msix_notify(pci_dev, v);
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return;
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}
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- if (msi_enabled(&xhci->pci_dev)) {
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+ if (msi_enabled(pci_dev)) {
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trace_usb_xhci_irq_msi(v);
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- msi_notify(&xhci->pci_dev, v);
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+ msi_notify(pci_dev, v);
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return;
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}
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@@ -793,6 +800,7 @@ static void xhci_die(XHCIState *xhci)
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static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
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{
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+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
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XHCIInterrupter *intr = &xhci->intr[v];
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XHCITRB ev_trb;
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dma_addr_t addr;
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@@ -811,7 +819,7 @@ static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
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ev_trb.status, ev_trb.control);
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addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
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- pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE);
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+ pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
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intr->er_ep_idx++;
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if (intr->er_ep_idx >= intr->er_size) {
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@@ -958,9 +966,11 @@ static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
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static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
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dma_addr_t *addr)
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{
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+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
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+
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while (1) {
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TRBType type;
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- pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE);
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+ pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
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trb->addr = ring->dequeue;
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trb->ccs = ring->ccs;
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le64_to_cpus(&trb->parameter);
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@@ -993,6 +1003,7 @@ static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
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static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
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{
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+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
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XHCITRB trb;
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int length = 0;
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dma_addr_t dequeue = ring->dequeue;
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@@ -1002,7 +1013,7 @@ static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
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while (1) {
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TRBType type;
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- pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE);
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+ pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
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le64_to_cpus(&trb.parameter);
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le32_to_cpus(&trb.status);
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le32_to_cpus(&trb.control);
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@@ -1054,7 +1065,7 @@ static void xhci_er_reset(XHCIState *xhci, int v)
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return;
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}
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dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
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- pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg));
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+ pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
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le32_to_cpus(&seg.addr_low);
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le32_to_cpus(&seg.addr_high);
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le32_to_cpus(&seg.size);
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@@ -1528,7 +1539,7 @@ static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
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int i;
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xfer->int_req = false;
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- pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count);
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+ pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
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for (i = 0; i < xfer->trb_count; i++) {
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XHCITRB *trb = &xfer->trbs[i];
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dma_addr_t addr;
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@@ -2144,7 +2155,7 @@ static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
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assert(slotid >= 1 && slotid <= xhci->numslots);
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dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
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- poctx = ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid);
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+ poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
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ictx = xhci_mask64(pictx);
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octx = xhci_mask64(poctx);
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@@ -2465,7 +2476,7 @@ static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
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/* TODO: actually implement real values here */
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bw_ctx[0] = 0;
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memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
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- pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
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+ pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
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return CC_SUCCESS;
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}
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@@ -2488,11 +2499,12 @@ static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
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static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
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{
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+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
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uint32_t buf[8];
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uint32_t obuf[8];
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dma_addr_t paddr = xhci_mask64(addr);
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- pci_dma_read(&xhci->pci_dev, paddr, &buf, 32);
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+ pci_dma_read(pci_dev, paddr, &buf, 32);
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memcpy(obuf, buf, sizeof(obuf));
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@@ -2508,7 +2520,7 @@ static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
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obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
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}
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958e1b |
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- pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32);
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+ pci_dma_write(pci_dev, paddr, &obuf, 32);
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}
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958e1b |
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958e1b |
static void xhci_process_commands(XHCIState *xhci)
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958e1b |
@@ -3372,10 +3384,10 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
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958e1b |
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XHCIState *xhci = XHCI(dev);
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958e1b |
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- xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */
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958e1b |
- xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
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958e1b |
- xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
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958e1b |
- xhci->pci_dev.config[0x60] = 0x30; /* release number */
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958e1b |
+ dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
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958e1b |
+ dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
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958e1b |
+ dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
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958e1b |
+ dev->config[0x60] = 0x30; /* release number */
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958e1b |
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958e1b |
usb_xhci_init(xhci);
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958e1b |
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958e1b |
@@ -3397,7 +3409,7 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
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958e1b |
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958e1b |
xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci);
|
|
|
958e1b |
|
|
|
958e1b |
- xhci->irq = xhci->pci_dev.irq[0];
|
|
|
958e1b |
+ xhci->irq = dev->irq[0];
|
|
|
958e1b |
|
|
|
958e1b |
memory_region_init(&xhci->mem, "xhci", LEN_REGS);
|
|
|
958e1b |
memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci,
|
|
|
958e1b |
@@ -3423,18 +3435,18 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
|
|
|
958e1b |
memory_region_add_subregion(&xhci->mem, offset, &port->mem);
|
|
|
958e1b |
}
|
|
|
958e1b |
|
|
|
958e1b |
- pci_register_bar(&xhci->pci_dev, 0,
|
|
|
958e1b |
+ pci_register_bar(dev, 0,
|
|
|
958e1b |
PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
|
|
|
958e1b |
&xhci->mem);
|
|
|
958e1b |
|
|
|
958e1b |
- ret = pcie_endpoint_cap_init(&xhci->pci_dev, 0xa0);
|
|
|
958e1b |
+ ret = pcie_endpoint_cap_init(dev, 0xa0);
|
|
|
958e1b |
assert(ret >= 0);
|
|
|
958e1b |
|
|
|
958e1b |
if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) {
|
|
|
958e1b |
- msi_init(&xhci->pci_dev, 0x70, xhci->numintrs, true, false);
|
|
|
958e1b |
+ msi_init(dev, 0x70, xhci->numintrs, true, false);
|
|
|
958e1b |
}
|
|
|
958e1b |
if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) {
|
|
|
958e1b |
- msix_init(&xhci->pci_dev, xhci->numintrs,
|
|
|
958e1b |
+ msix_init(dev, xhci->numintrs,
|
|
|
958e1b |
&xhci->mem, 0, OFF_MSIX_TABLE,
|
|
|
958e1b |
&xhci->mem, 0, OFF_MSIX_PBA,
|
|
|
958e1b |
0x90);
|
|
|
958e1b |
@@ -3446,6 +3458,7 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
|
|
|
958e1b |
static int usb_xhci_post_load(void *opaque, int version_id)
|
|
|
958e1b |
{
|
|
|
958e1b |
XHCIState *xhci = opaque;
|
|
|
958e1b |
+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
|
|
|
958e1b |
XHCISlot *slot;
|
|
|
958e1b |
XHCIEPContext *epctx;
|
|
|
958e1b |
dma_addr_t dcbaap, pctx;
|
|
|
958e1b |
@@ -3461,7 +3474,7 @@ static int usb_xhci_post_load(void *opaque, int version_id)
|
|
|
958e1b |
continue;
|
|
|
958e1b |
}
|
|
|
958e1b |
slot->ctx =
|
|
|
958e1b |
- xhci_mask64(ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid));
|
|
|
958e1b |
+ xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
|
|
|
958e1b |
xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
|
|
|
958e1b |
slot->uport = xhci_lookup_uport(xhci, slot_ctx);
|
|
|
958e1b |
assert(slot->uport && slot->uport->dev);
|
|
|
958e1b |
@@ -3486,9 +3499,9 @@ static int usb_xhci_post_load(void *opaque, int version_id)
|
|
|
958e1b |
|
|
|
958e1b |
for (intr = 0; intr < xhci->numintrs; intr++) {
|
|
|
958e1b |
if (xhci->intr[intr].msix_used) {
|
|
|
958e1b |
- msix_vector_use(&xhci->pci_dev, intr);
|
|
|
958e1b |
+ msix_vector_use(pci_dev, intr);
|
|
|
958e1b |
} else {
|
|
|
958e1b |
- msix_vector_unuse(&xhci->pci_dev, intr);
|
|
|
958e1b |
+ msix_vector_unuse(pci_dev, intr);
|
|
|
958e1b |
}
|
|
|
958e1b |
}
|
|
|
958e1b |
|
|
|
958e1b |
@@ -3593,8 +3606,8 @@ static const VMStateDescription vmstate_xhci = {
|
|
|
958e1b |
.version_id = 1,
|
|
|
958e1b |
.post_load = usb_xhci_post_load,
|
|
|
958e1b |
.fields = (VMStateField[]) {
|
|
|
958e1b |
- VMSTATE_PCIE_DEVICE(pci_dev, XHCIState),
|
|
|
958e1b |
- VMSTATE_MSIX(pci_dev, XHCIState),
|
|
|
958e1b |
+ VMSTATE_PCIE_DEVICE(parent_obj, XHCIState),
|
|
|
958e1b |
+ VMSTATE_MSIX(parent_obj, XHCIState),
|
|
|
958e1b |
|
|
|
958e1b |
VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
|
|
|
958e1b |
vmstate_xhci_port, XHCIPort),
|
|
|
958e1b |
--
|
|
|
958e1b |
1.8.3.1
|
|
|
958e1b |
|