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Blame SOURCES/kvm-target-i386-remove-tabs-from-target-i386-cpu.h.patch

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From 1f49705e06366e1c2fa2b2c77497ed33ca1c6a30 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Mon, 23 Sep 2013 17:06:11 +0200
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Subject: [PATCH 01/29] target-i386: remove tabs from target-i386/cpu.h
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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Message-id: <1379955972-3080-2-git-send-email-pbonzini@redhat.com>
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Patchwork-id: 54486
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O-Subject: [RHEL 7.0 qemu-kvm PATCH 1/2] target-i386: remove tabs from target-i386/cpu.h
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Bugzilla: 928867
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RH-Acked-by: Juan Quintela <quintela@redhat.com>
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RH-Acked-by: Marcelo Tosatti <mtosatti@redhat.com>
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RH-Acked-by: Bandan Das <bsd@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry-picked from commit e4a09c9637f13a744ad7e2bc5223df05ac582c0d)
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---
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 target-i386/cpu.h | 192 +++++++++++++++++++++++++++---------------------------
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 1 file changed, 96 insertions(+), 96 deletions(-)
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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 target-i386/cpu.h |  192 ++++++++++++++++++++++++++--------------------------
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 1 files changed, 96 insertions(+), 96 deletions(-)
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diff --git a/target-i386/cpu.h b/target-i386/cpu.h
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index 058c57f..74c7899 100644
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--- a/target-i386/cpu.h
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+++ b/target-i386/cpu.h
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@@ -37,9 +37,9 @@
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 #define TARGET_HAS_ICE 1
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 #ifdef TARGET_X86_64
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-#define ELF_MACHINE	EM_X86_64
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+#define ELF_MACHINE     EM_X86_64
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 #else
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-#define ELF_MACHINE	EM_386
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+#define ELF_MACHINE     EM_386
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 #endif
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 #define CPUArchState struct CPUX86State
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@@ -98,10 +98,10 @@
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 #define DESC_TSS_BUSY_MASK (1 << 9)
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 /* eflags masks */
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-#define CC_C   	0x0001
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-#define CC_P 	0x0004
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-#define CC_A	0x0010
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-#define CC_Z	0x0040
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+#define CC_C    0x0001
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+#define CC_P    0x0004
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+#define CC_A    0x0010
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+#define CC_Z    0x0040
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 #define CC_S    0x0080
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 #define CC_O    0x0800
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@@ -109,14 +109,14 @@
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 #define IOPL_SHIFT 12
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 #define VM_SHIFT   17
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-#define TF_MASK 		0x00000100
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-#define IF_MASK 		0x00000200
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-#define DF_MASK 		0x00000400
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-#define IOPL_MASK		0x00003000
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-#define NT_MASK	         	0x00004000
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-#define RF_MASK			0x00010000
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-#define VM_MASK			0x00020000
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-#define AC_MASK			0x00040000
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+#define TF_MASK                 0x00000100
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+#define IF_MASK                 0x00000200
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+#define DF_MASK                 0x00000400
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+#define IOPL_MASK               0x00003000
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+#define NT_MASK                 0x00004000
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+#define RF_MASK                 0x00010000
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+#define VM_MASK                 0x00020000
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+#define AC_MASK                 0x00040000
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 #define VIF_MASK                0x00080000
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 #define VIP_MASK                0x00100000
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 #define ID_MASK                 0x00200000
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@@ -238,28 +238,28 @@
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 #define DR7_TYPE_IO_RW       0x2
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 #define DR7_TYPE_DATA_RW     0x3
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-#define PG_PRESENT_BIT	0
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-#define PG_RW_BIT	1
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-#define PG_USER_BIT	2
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-#define PG_PWT_BIT	3
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-#define PG_PCD_BIT	4
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-#define PG_ACCESSED_BIT	5
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-#define PG_DIRTY_BIT	6
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-#define PG_PSE_BIT	7
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-#define PG_GLOBAL_BIT	8
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-#define PG_NX_BIT	63
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+#define PG_PRESENT_BIT  0
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+#define PG_RW_BIT       1
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+#define PG_USER_BIT     2
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+#define PG_PWT_BIT      3
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+#define PG_PCD_BIT      4
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+#define PG_ACCESSED_BIT 5
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+#define PG_DIRTY_BIT    6
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+#define PG_PSE_BIT      7
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+#define PG_GLOBAL_BIT   8
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+#define PG_NX_BIT       63
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 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
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-#define PG_RW_MASK	 (1 << PG_RW_BIT)
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-#define PG_USER_MASK	 (1 << PG_USER_BIT)
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-#define PG_PWT_MASK	 (1 << PG_PWT_BIT)
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-#define PG_PCD_MASK	 (1 << PG_PCD_BIT)
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+#define PG_RW_MASK       (1 << PG_RW_BIT)
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+#define PG_USER_MASK     (1 << PG_USER_BIT)
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+#define PG_PWT_MASK      (1 << PG_PWT_BIT)
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+#define PG_PCD_MASK      (1 << PG_PCD_BIT)
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 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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-#define PG_DIRTY_MASK	 (1 << PG_DIRTY_BIT)
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-#define PG_PSE_MASK	 (1 << PG_PSE_BIT)
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-#define PG_GLOBAL_MASK	 (1 << PG_GLOBAL_BIT)
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+#define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
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+#define PG_PSE_MASK      (1 << PG_PSE_BIT)
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+#define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
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 #define PG_HI_USER_MASK  0x7ff0000000000000LL
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-#define PG_NX_MASK	 (1LL << PG_NX_BIT)
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+#define PG_NX_MASK       (1LL << PG_NX_BIT)
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 #define PG_ERROR_W_BIT     1
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@@ -269,32 +269,32 @@
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 #define PG_ERROR_RSVD_MASK 0x08
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 #define PG_ERROR_I_D_MASK  0x10
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-#define MCG_CTL_P	(1ULL<<8)   /* MCG_CAP register available */
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-#define MCG_SER_P	(1ULL<<24) /* MCA recovery/new status bits */
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+#define MCG_CTL_P       (1ULL<<8)   /* MCG_CAP register available */
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+#define MCG_SER_P       (1ULL<<24) /* MCA recovery/new status bits */
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-#define MCE_CAP_DEF	(MCG_CTL_P|MCG_SER_P)
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-#define MCE_BANKS_DEF	10
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+#define MCE_CAP_DEF     (MCG_CTL_P|MCG_SER_P)
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+#define MCE_BANKS_DEF   10
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-#define MCG_STATUS_RIPV	(1ULL<<0)   /* restart ip valid */
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-#define MCG_STATUS_EIPV	(1ULL<<1)   /* ip points to correct instruction */
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-#define MCG_STATUS_MCIP	(1ULL<<2)   /* machine check in progress */
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+#define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
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+#define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
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+#define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
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-#define MCI_STATUS_VAL	(1ULL<<63)  /* valid error */
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-#define MCI_STATUS_OVER	(1ULL<<62)  /* previous errors lost */
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-#define MCI_STATUS_UC	(1ULL<<61)  /* uncorrected error */
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-#define MCI_STATUS_EN	(1ULL<<60)  /* error enabled */
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-#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
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-#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
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-#define MCI_STATUS_PCC	(1ULL<<57)  /* processor context corrupt */
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-#define MCI_STATUS_S	(1ULL<<56)  /* Signaled machine check */
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-#define MCI_STATUS_AR	(1ULL<<55)  /* Action required */
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+#define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
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+#define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
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+#define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
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+#define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
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+#define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
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+#define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
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+#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
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+#define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
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+#define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
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 /* MISC register defines */
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-#define MCM_ADDR_SEGOFF	0	/* segment offset */
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-#define MCM_ADDR_LINEAR	1	/* linear address */
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-#define MCM_ADDR_PHYS	2	/* physical address */
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-#define MCM_ADDR_MEM	3	/* memory address */
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-#define MCM_ADDR_GENERIC 7	/* generic */
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+#define MCM_ADDR_SEGOFF  0      /* segment offset */
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+#define MCM_ADDR_LINEAR  1      /* linear address */
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+#define MCM_ADDR_PHYS    2      /* physical address */
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+#define MCM_ADDR_MEM     3      /* memory address */
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+#define MCM_ADDR_GENERIC 7      /* generic */
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 #define MSR_IA32_TSC                    0x10
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 #define MSR_IA32_APICBASE               0x1b
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@@ -304,10 +304,10 @@
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 #define MSR_TSC_ADJUST                  0x0000003b
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 #define MSR_IA32_TSCDEADLINE            0x6e0
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-#define MSR_MTRRcap			0xfe
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-#define MSR_MTRRcap_VCNT		8
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-#define MSR_MTRRcap_FIXRANGE_SUPPORT	(1 << 8)
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-#define MSR_MTRRcap_WC_SUPPORTED	(1 << 10)
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+#define MSR_MTRRcap                     0xfe
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+#define MSR_MTRRcap_VCNT                8
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+#define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
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+#define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
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 #define MSR_IA32_SYSENTER_CS            0x174
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 #define MSR_IA32_SYSENTER_ESP           0x175
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@@ -319,33 +319,33 @@
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 #define MSR_IA32_PERF_STATUS            0x198
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-#define MSR_IA32_MISC_ENABLE		0x1a0
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+#define MSR_IA32_MISC_ENABLE            0x1a0
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 /* Indicates good rep/movs microcode on some processors: */
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 #define MSR_IA32_MISC_ENABLE_DEFAULT    1
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-#define MSR_MTRRphysBase(reg)		(0x200 + 2 * (reg))
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-#define MSR_MTRRphysMask(reg)		(0x200 + 2 * (reg) + 1)
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-
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-#define MSR_MTRRfix64K_00000		0x250
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-#define MSR_MTRRfix16K_80000		0x258
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-#define MSR_MTRRfix16K_A0000		0x259
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-#define MSR_MTRRfix4K_C0000		0x268
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-#define MSR_MTRRfix4K_C8000		0x269
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-#define MSR_MTRRfix4K_D0000		0x26a
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-#define MSR_MTRRfix4K_D8000		0x26b
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-#define MSR_MTRRfix4K_E0000		0x26c
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-#define MSR_MTRRfix4K_E8000		0x26d
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-#define MSR_MTRRfix4K_F0000		0x26e
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-#define MSR_MTRRfix4K_F8000		0x26f
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+#define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
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+#define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
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+
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+#define MSR_MTRRfix64K_00000            0x250
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+#define MSR_MTRRfix16K_80000            0x258
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+#define MSR_MTRRfix16K_A0000            0x259
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+#define MSR_MTRRfix4K_C0000             0x268
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+#define MSR_MTRRfix4K_C8000             0x269
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+#define MSR_MTRRfix4K_D0000             0x26a
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+#define MSR_MTRRfix4K_D8000             0x26b
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+#define MSR_MTRRfix4K_E0000             0x26c
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+#define MSR_MTRRfix4K_E8000             0x26d
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+#define MSR_MTRRfix4K_F0000             0x26e
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+#define MSR_MTRRfix4K_F8000             0x26f
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 #define MSR_PAT                         0x277
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-#define MSR_MTRRdefType			0x2ff
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+#define MSR_MTRRdefType                 0x2ff
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-#define MSR_MC0_CTL			0x400
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-#define MSR_MC0_STATUS			0x401
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-#define MSR_MC0_ADDR			0x402
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-#define MSR_MC0_MISC			0x403
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+#define MSR_MC0_CTL                     0x400
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+#define MSR_MC0_STATUS                  0x401
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+#define MSR_MC0_ADDR                    0x402
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+#define MSR_MC0_MISC                    0x403
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 #define MSR_EFER                        0xc0000080
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@@ -549,24 +549,24 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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 #define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
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 #define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
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-#define EXCP00_DIVZ	0
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-#define EXCP01_DB	1
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-#define EXCP02_NMI	2
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-#define EXCP03_INT3	3
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-#define EXCP04_INTO	4
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-#define EXCP05_BOUND	5
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-#define EXCP06_ILLOP	6
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-#define EXCP07_PREX	7
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-#define EXCP08_DBLE	8
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-#define EXCP09_XERR	9
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-#define EXCP0A_TSS	10
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-#define EXCP0B_NOSEG	11
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-#define EXCP0C_STACK	12
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-#define EXCP0D_GPF	13
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-#define EXCP0E_PAGE	14
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-#define EXCP10_COPR	16
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-#define EXCP11_ALGN	17
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-#define EXCP12_MCHK	18
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+#define EXCP00_DIVZ     0
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+#define EXCP01_DB       1
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+#define EXCP02_NMI      2
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+#define EXCP03_INT3     3
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+#define EXCP04_INTO     4
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+#define EXCP05_BOUND    5
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+#define EXCP06_ILLOP    6
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+#define EXCP07_PREX     7
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+#define EXCP08_DBLE     8
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+#define EXCP09_XERR     9
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+#define EXCP0A_TSS      10
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+#define EXCP0B_NOSEG    11
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+#define EXCP0C_STACK    12
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+#define EXCP0D_GPF      13
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+#define EXCP0E_PAGE     14
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+#define EXCP10_COPR     16
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+#define EXCP11_ALGN     17
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+#define EXCP12_MCHK     18
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 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
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                                  for syscall instruction */
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@@ -1085,7 +1085,7 @@ static inline CPUX86State *cpu_init(const char *cpu_model)
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 #define cpu_gen_code cpu_x86_gen_code
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 #define cpu_signal_handler cpu_x86_signal_handler
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 #define cpu_list x86_cpu_list
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-#define cpudef_setup	x86_cpudef_setup
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+#define cpudef_setup x86_cpudef_setup
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 /* MMU modes definitions */
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 #define MMU_MODE0_SUFFIX _kernel
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-- 
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1.7.1
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