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From 5567938d29bf8a0ce451e59a8db009c12ab3444c Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Thu, 25 Jun 2015 19:31:29 +0200
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Subject: [PATCH 09/10] target-i386: add Intel AVX-512 support
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Message-id: <1435260689-9556-9-git-send-email-ehabkost@redhat.com>
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Patchwork-id: 66506
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O-Subject: [RHEL-7.2 qemu-kvm PATCH 8/8] target-i386: add Intel AVX-512 support
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Bugzilla: 1233350
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Bandan Das <bsd@redhat.com>
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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Add AVX512 feature bits, register definition and corresponding
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xsave/vmstate support.
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Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 9aecd6f8aef653cea58932f06a2740299dbe5fd3)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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Conflicts:
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	target-i386/cpu.h
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	target-i386/machine.c
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---
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 target-i386/cpu.c     | 10 ++++--
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 target-i386/cpu.h     | 61 ++++++++++++++++++++++++++++++++++++
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 target-i386/kvm.c     | 19 +++++++++++
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 target-i386/machine.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++++
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 4 files changed, 175 insertions(+), 2 deletions(-)
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diff --git a/target-i386/cpu.c b/target-i386/cpu.c
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index fe60c33..06efe17 100644
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--- a/target-i386/cpu.c
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+++ b/target-i386/cpu.c
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@@ -146,8 +146,8 @@ static const char *svm_feature_name[] = {
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 static const char *cpuid_7_0_ebx_feature_name[] = {
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     "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
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     "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
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-    NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
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-    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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+    "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
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+    NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
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 };
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 typedef struct FeatureWordInfo {
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@@ -228,6 +228,12 @@ static const ExtSaveArea ext_save_areas[] = {
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             .offset = 0x3c0, .size = 0x40  },
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     [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
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             .offset = 0x400, .size = 0x40  },
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+    [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
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+            .offset = 0x440, .size = 0x40 },
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+    [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
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+            .offset = 0x480, .size = 0x200 },
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+    [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
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+            .offset = 0x680, .size = 0x400 },
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 };
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 const char *get_register_name_32(unsigned int reg)
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diff --git a/target-i386/cpu.h b/target-i386/cpu.h
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index fc1e42e..61e9b86 100644
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--- a/target-i386/cpu.h
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+++ b/target-i386/cpu.h
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@@ -390,6 +390,9 @@
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 #define XSTATE_YMM                      (1ULL << 2)
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 #define XSTATE_BNDREGS                  (1ULL << 3)
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 #define XSTATE_BNDCSR                   (1ULL << 4)
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+#define XSTATE_OPMASK                   (1ULL << 5)
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+#define XSTATE_ZMM_Hi256                (1ULL << 6)
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+#define XSTATE_Hi16_ZMM                 (1ULL << 7)
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 /* CPUID feature words */
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@@ -554,9 +557,13 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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 #define CPUID_7_0_EBX_INVPCID  (1U << 10)
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 #define CPUID_7_0_EBX_RTM      (1U << 11)
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 #define CPUID_7_0_EBX_MPX      (1U << 14)
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+#define CPUID_7_0_EBX_AVX512F  (1U << 16) /* AVX-512 Foundation */
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 #define CPUID_7_0_EBX_RDSEED   (1U << 18)
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 #define CPUID_7_0_EBX_ADX      (1U << 19)
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 #define CPUID_7_0_EBX_SMAP     (1U << 20)
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+#define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
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+#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
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+#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
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 #define CPUID_VENDOR_SZ      12
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@@ -697,6 +704,24 @@ typedef union {
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 } XMMReg;
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 typedef union {
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+    uint8_t _b[32];
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+    uint16_t _w[16];
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+    uint32_t _l[8];
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+    uint64_t _q[4];
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+    float32 _s[8];
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+    float64 _d[4];
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+} YMMReg;
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+
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+typedef union {
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+    uint8_t _b[64];
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+    uint16_t _w[32];
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+    uint32_t _l[16];
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+    uint64_t _q[8];
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+    float32 _s[16];
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+    float64 _d[8];
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+} ZMMReg;
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+
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+typedef union {
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     uint8_t _b[8];
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     uint16_t _w[4];
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     uint32_t _l[2];
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@@ -715,6 +740,20 @@ typedef struct BNDCSReg {
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 } BNDCSReg;
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 #ifdef HOST_WORDS_BIGENDIAN
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+#define ZMM_B(n) _b[63 - (n)]
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+#define ZMM_W(n) _w[31 - (n)]
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+#define ZMM_L(n) _l[15 - (n)]
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+#define ZMM_S(n) _s[15 - (n)]
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+#define ZMM_Q(n) _q[7 - (n)]
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+#define ZMM_D(n) _d[7 - (n)]
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+
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+#define YMM_B(n) _b[31 - (n)]
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+#define YMM_W(n) _w[15 - (n)]
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+#define YMM_L(n) _l[7 - (n)]
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+#define YMM_S(n) _s[7 - (n)]
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+#define YMM_Q(n) _q[3 - (n)]
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+#define YMM_D(n) _d[3 - (n)]
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+
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 #define XMM_B(n) _b[15 - (n)]
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 #define XMM_W(n) _w[7 - (n)]
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 #define XMM_L(n) _l[3 - (n)]
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@@ -727,6 +766,20 @@ typedef struct BNDCSReg {
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 #define MMX_L(n) _l[1 - (n)]
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 #define MMX_S(n) _s[1 - (n)]
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 #else
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+#define ZMM_B(n) _b[n]
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+#define ZMM_W(n) _w[n]
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+#define ZMM_L(n) _l[n]
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+#define ZMM_S(n) _s[n]
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+#define ZMM_Q(n) _q[n]
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+#define ZMM_D(n) _d[n]
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+
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+#define YMM_B(n) _b[n]
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+#define YMM_W(n) _w[n]
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+#define YMM_L(n) _l[n]
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+#define YMM_S(n) _s[n]
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+#define YMM_Q(n) _q[n]
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+#define YMM_D(n) _d[n]
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+
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 #define XMM_B(n) _b[n]
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 #define XMM_W(n) _w[n]
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 #define XMM_L(n) _l[n]
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@@ -765,6 +818,8 @@ typedef struct {
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 #define NB_MMU_MODES 3
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+#define NB_OPMASK_REGS 8
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+
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 typedef enum TPRAccess {
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     TPR_ACCESS_READ,
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     TPR_ACCESS_WRITE,
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@@ -826,6 +881,12 @@ typedef struct CPUX86State {
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     XMMReg ymmh_regs[CPU_NB_REGS];
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+    uint64_t opmask_regs[NB_OPMASK_REGS];
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+    YMMReg zmmh_regs[CPU_NB_REGS];
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+#ifdef TARGET_X86_64
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+    ZMMReg hi16_zmm_regs[CPU_NB_REGS];
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+#endif
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+
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     /* sysenter registers */
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     uint32_t sysenter_cs;
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     target_ulong sysenter_esp;
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diff --git a/target-i386/kvm.c b/target-i386/kvm.c
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index bbbbac0..c91bfb8 100644
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--- a/target-i386/kvm.c
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+++ b/target-i386/kvm.c
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@@ -995,6 +995,9 @@ static int kvm_put_fpu(X86CPU *cpu)
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 #define XSAVE_YMMH_SPACE  144
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 #define XSAVE_BNDREGS     240
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 #define XSAVE_BNDCSR      256
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+#define XSAVE_OPMASK      272
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+#define XSAVE_ZMM_Hi256   288
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+#define XSAVE_Hi16_ZMM    416
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 static int kvm_put_xsave(X86CPU *cpu)
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 {
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@@ -1031,6 +1034,14 @@ static int kvm_put_xsave(X86CPU *cpu)
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             sizeof env->bnd_regs);
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     memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
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             sizeof(env->bndcs_regs));
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+    memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
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+            sizeof env->opmask_regs);
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+    memcpy(&xsave->region[XSAVE_ZMM_Hi256], env->zmmh_regs,
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+            sizeof env->zmmh_regs);
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+#ifdef TARGET_X86_64
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+    memcpy(&xsave->region[XSAVE_Hi16_ZMM], env->hi16_zmm_regs,
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+            sizeof env->hi16_zmm_regs);
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+#endif
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     r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
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     return r;
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 }
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@@ -1354,6 +1365,14 @@ static int kvm_get_xsave(X86CPU *cpu)
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             sizeof env->bnd_regs);
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     memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
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             sizeof(env->bndcs_regs));
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+    memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
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+            sizeof env->opmask_regs);
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+    memcpy(env->zmmh_regs, &xsave->region[XSAVE_ZMM_Hi256],
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+            sizeof env->zmmh_regs);
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+#ifdef TARGET_X86_64
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+    memcpy(env->hi16_zmm_regs, &xsave->region[XSAVE_Hi16_ZMM],
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+            sizeof env->hi16_zmm_regs);
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+#endif
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     return 0;
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 }
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diff --git a/target-i386/machine.c b/target-i386/machine.c
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index b6be606..2c97002 100644
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--- a/target-i386/machine.c
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+++ b/target-i386/machine.c
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@@ -63,6 +63,44 @@ static const VMStateDescription vmstate_ymmh_reg = {
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 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v)                         \
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     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg)
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+static const VMStateDescription vmstate_zmmh_reg = {
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+    .name = "zmmh_reg",
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+    .version_id = 1,
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+    .minimum_version_id = 1,
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+    .fields = (VMStateField[]) {
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+        VMSTATE_UINT64(YMM_Q(0), YMMReg),
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+        VMSTATE_UINT64(YMM_Q(1), YMMReg),
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+        VMSTATE_UINT64(YMM_Q(2), YMMReg),
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+        VMSTATE_UINT64(YMM_Q(3), YMMReg),
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+        VMSTATE_END_OF_LIST()
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+    }
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+};
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+
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+#define VMSTATE_ZMMH_REGS_VARS(_field, _state, _n)                             \
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+    VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_zmmh_reg, YMMReg)
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+
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+#ifdef TARGET_X86_64
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+static const VMStateDescription vmstate_hi16_zmm_reg = {
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+    .name = "hi16_zmm_reg",
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+    .version_id = 1,
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+    .minimum_version_id = 1,
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+    .fields = (VMStateField[]) {
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+        VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
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+        VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
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+        VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
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+        VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
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+        VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
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+        VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
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+        VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
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+        VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
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+        VMSTATE_END_OF_LIST()
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+    }
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+};
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+
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+#define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _n)                         \
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+    VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_hi16_zmm_reg, ZMMReg)
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+#endif
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+
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 static const VMStateDescription vmstate_bnd_regs = {
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     .name = "bnd_regs",
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     .version_id = 1,
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@@ -620,6 +658,52 @@ static const VMStateDescription vmstate_mpx = {
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     }
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 };
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+static bool avx512_needed(void *opaque)
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+{
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+    X86CPU *cpu = opaque;
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+    CPUX86State *env = &cpu->env;
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+    unsigned int i;
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+
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+    for (i = 0; i < NB_OPMASK_REGS; i++) {
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+        if (env->opmask_regs[i]) {
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+            return true;
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+        }
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+    }
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+
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+    for (i = 0; i < CPU_NB_REGS; i++) {
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+#define ENV_ZMMH(reg, field) (env->zmmh_regs[reg].YMM_Q(field))
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+        if (ENV_ZMMH(i, 0) || ENV_ZMMH(i, 1) ||
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+            ENV_ZMMH(i, 2) || ENV_ZMMH(i, 3)) {
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+            return true;
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+        }
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+#ifdef TARGET_X86_64
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+#define ENV_Hi16_ZMM(reg, field) (env->hi16_zmm_regs[reg].ZMM_Q(field))
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+        if (ENV_Hi16_ZMM(i, 0) || ENV_Hi16_ZMM(i, 1) ||
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+            ENV_Hi16_ZMM(i, 2) || ENV_Hi16_ZMM(i, 3) ||
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+            ENV_Hi16_ZMM(i, 4) || ENV_Hi16_ZMM(i, 5) ||
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+            ENV_Hi16_ZMM(i, 6) || ENV_Hi16_ZMM(i, 7)) {
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+            return true;
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+        }
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+#endif
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+    }
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+
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+    return false;
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+}
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+
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+static const VMStateDescription vmstate_avx512 = {
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+    .name = "cpu/avx512",
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+    .version_id = 1,
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+    .minimum_version_id = 1,
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+    .fields = (VMStateField[]) {
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+        VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS),
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+        VMSTATE_ZMMH_REGS_VARS(env.zmmh_regs, X86CPU, CPU_NB_REGS),
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+#ifdef TARGET_X86_64
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+        VMSTATE_Hi16_ZMM_REGS_VARS(env.hi16_zmm_regs, X86CPU, CPU_NB_REGS),
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+#endif
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+        VMSTATE_END_OF_LIST()
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+    }
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+};
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+
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 const VMStateDescription vmstate_x86_cpu = {
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     .name = "cpu",
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     .version_id = 12,
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@@ -763,6 +847,9 @@ const VMStateDescription vmstate_x86_cpu = {
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         } , {
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             .vmsd = &vmstate_mpx,
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             .needed = mpx_needed,
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+        }, {
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+            .vmsd = &vmstate_avx512,
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+            .needed = avx512_needed,
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         } , {
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             /* empty */
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         }
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-- 
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1.8.3.1
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