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From 0c9168510f4ddbdec3b0a88095db2e8f3f0aeef7 Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Thu, 25 Jun 2015 19:31:23 +0200
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Subject: [PATCH 03/10] target-i386: Intel MPX
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Message-id: <1435260689-9556-3-git-send-email-ehabkost@redhat.com>
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Patchwork-id: 66500
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O-Subject: [RHEL-7.2 qemu-kvm PATCH 2/8] target-i386: Intel MPX
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Bugzilla: 1233350
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Bandan Das <bsd@redhat.com>
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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From: Liu Jinsong <jinsong.liu@intel.com>
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1233350
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Add some MPX related definiation, and hardcode sizes and offsets
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of xsave features 3 and 4. It also add corresponding part to
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kvm_get/put_xsave, and vmstate.
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Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 79e9ebebbf2a00c46fcedb6dc7dd5e12bbd30216)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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Conflicts:
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	target-i386/kvm.c
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	target-i386/machine.c
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---
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 target-i386/cpu.c     |  4 ++++
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 target-i386/cpu.h     | 25 ++++++++++++++++++++++---
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 target-i386/kvm.c     | 24 ++++++++++++++++++++++++
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 target-i386/machine.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
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 4 files changed, 101 insertions(+), 3 deletions(-)
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diff --git a/target-i386/cpu.c b/target-i386/cpu.c
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index 0fd100f..a9e80d9 100644
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--- a/target-i386/cpu.c
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+++ b/target-i386/cpu.c
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@@ -224,6 +224,10 @@ typedef struct ExtSaveArea {
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 static const ExtSaveArea ext_save_areas[] = {
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     [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
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             .offset = 0x240, .size = 0x100 },
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+    [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
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+            .offset = 0x3c0, .size = 0x40  },
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+    [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
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+            .offset = 0x400, .size = 0x10  },
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 };
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 const char *get_register_name_32(unsigned int reg)
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diff --git a/target-i386/cpu.h b/target-i386/cpu.h
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index e9edd3d..7ebdbb3 100644
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--- a/target-i386/cpu.h
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+++ b/target-i386/cpu.h
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@@ -383,9 +383,14 @@
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 #define MSR_VM_HSAVE_PA                 0xc0010117
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-#define XSTATE_FP                       1
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-#define XSTATE_SSE                      2
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-#define XSTATE_YMM                      4
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+#define MSR_IA32_BNDCFGS                0x00000d90
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+
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+#define XSTATE_FP                       (1ULL << 0)
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+#define XSTATE_SSE                      (1ULL << 1)
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+#define XSTATE_YMM                      (1ULL << 2)
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+#define XSTATE_BNDREGS                  (1ULL << 3)
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+#define XSTATE_BNDCSR                   (1ULL << 4)
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+
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 /* CPUID feature words */
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 typedef enum FeatureWord {
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@@ -548,6 +553,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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 #define CPUID_7_0_EBX_ERMS     (1 << 9)
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 #define CPUID_7_0_EBX_INVPCID  (1 << 10)
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 #define CPUID_7_0_EBX_RTM      (1 << 11)
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+#define CPUID_7_0_EBX_MPX      (1 << 14)
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 #define CPUID_7_0_EBX_RDSEED   (1 << 18)
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 #define CPUID_7_0_EBX_ADX      (1 << 19)
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 #define CPUID_7_0_EBX_SMAP     (1 << 20)
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@@ -698,6 +704,16 @@ typedef union {
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     uint64_t q;
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 } MMXReg;
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+typedef struct BNDReg {
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+    uint64_t lb;
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+    uint64_t ub;
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+} BNDReg;
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+
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+typedef struct BNDCSReg {
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+    uint64_t cfgu;
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+    uint64_t sts;
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+} BNDCSReg;
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+
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 #ifdef HOST_WORDS_BIGENDIAN
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 #define XMM_B(n) _b[15 - (n)]
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 #define XMM_W(n) _w[7 - (n)]
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@@ -918,6 +934,9 @@ typedef struct CPUX86State {
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     uint64_t xstate_bv;
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     XMMReg ymmh_regs[CPU_NB_REGS];
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+    BNDReg bnd_regs[4];
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+    BNDCSReg bndcs_regs;
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+    uint64_t msr_bndcfgs;
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     uint64_t xcr0;
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diff --git a/target-i386/kvm.c b/target-i386/kvm.c
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index 97ae345..6d9aa63 100644
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--- a/target-i386/kvm.c
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+++ b/target-i386/kvm.c
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@@ -68,6 +68,7 @@ static bool has_msr_tsc_deadline;
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 static bool has_msr_async_pf_en;
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 static bool has_msr_pv_eoi_en;
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 static bool has_msr_misc_enable;
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+static bool has_msr_bndcfgs;
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 static bool has_msr_kvm_steal_time;
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 static int lm_capable_kernel;
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 static bool has_msr_hv_hypercall;
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@@ -785,6 +786,10 @@ static int kvm_get_supported_msrs(KVMState *s)
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                     has_msr_misc_enable = true;
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                     continue;
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                 }
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+                if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
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+                    has_msr_bndcfgs = true;
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+                    continue;
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+                }
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             }
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         }
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@@ -988,6 +993,8 @@ static int kvm_put_fpu(X86CPU *cpu)
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 #define XSAVE_XMM_SPACE   40
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 #define XSAVE_XSTATE_BV   128
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 #define XSAVE_YMMH_SPACE  144
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+#define XSAVE_BNDREGS     240
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+#define XSAVE_BNDCSR      256
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 static int kvm_put_xsave(X86CPU *cpu)
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 {
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@@ -1020,6 +1027,10 @@ static int kvm_put_xsave(X86CPU *cpu)
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     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
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     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
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             sizeof env->ymmh_regs);
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+    memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
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+            sizeof env->bnd_regs);
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+    memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
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+            sizeof(env->bndcs_regs));
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     r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
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     return r;
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 }
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@@ -1255,6 +1266,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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                                   MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
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             }
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         }
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+        if (has_msr_bndcfgs) {
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+            kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
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+        }
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     }
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     if (env->mcg_cap) {
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         int i;
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@@ -1336,6 +1350,10 @@ static int kvm_get_xsave(X86CPU *cpu)
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     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
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     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
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             sizeof env->ymmh_regs);
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+    memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
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+            sizeof env->bnd_regs);
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+    memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
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+            sizeof(env->bndcs_regs));
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     return 0;
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 }
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@@ -1479,6 +1497,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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     if (has_msr_misc_enable) {
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         msrs[n++].index = MSR_IA32_MISC_ENABLE;
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     }
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+    if (has_msr_bndcfgs) {
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+        msrs[n++].index = MSR_IA32_BNDCFGS;
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+    }
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     if (!env->tsc_valid) {
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         msrs[n++].index = MSR_IA32_TSC;
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@@ -1620,6 +1641,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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         case MSR_IA32_MISC_ENABLE:
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             env->msr_ia32_misc_enable = msrs[i].data;
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             break;
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+        case MSR_IA32_BNDCFGS:
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+            env->msr_bndcfgs = msrs[i].data;
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+            break;
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         default:
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             if (msrs[i].index >= MSR_MC0_CTL &&
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                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
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diff --git a/target-i386/machine.c b/target-i386/machine.c
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index 4c1ead4..b6be606 100644
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--- a/target-i386/machine.c
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+++ b/target-i386/machine.c
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@@ -63,6 +63,21 @@ static const VMStateDescription vmstate_ymmh_reg = {
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 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v)                         \
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     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg)
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+static const VMStateDescription vmstate_bnd_regs = {
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+    .name = "bnd_regs",
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+    .version_id = 1,
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+    .minimum_version_id = 1,
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+    .minimum_version_id_old = 1,
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+    .fields      = (VMStateField[]) {
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+        VMSTATE_UINT64(lb, BNDReg),
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+        VMSTATE_UINT64(ub, BNDReg),
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+        VMSTATE_END_OF_LIST()
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+    }
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+};
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+
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+#define VMSTATE_BND_REGS(_field, _state, _n)          \
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+    VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
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+
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 static const VMStateDescription vmstate_mtrr_var = {
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     .name = "mtrr_var",
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     .version_id = 1,
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@@ -572,6 +587,39 @@ static const VMStateDescription vmstate_msr_hyperv_time = {
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     }
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 };
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+static bool mpx_needed(void *opaque)
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+{
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+    X86CPU *cpu = opaque;
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+    CPUX86State *env = &cpu->env;
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+    unsigned int i;
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+
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+    for (i = 0; i < 4; i++) {
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+        if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) {
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+            return true;
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+        }
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+    }
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+
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+    if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) {
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+        return true;
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+    }
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+
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+    return !!env->msr_bndcfgs;
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+}
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+
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+static const VMStateDescription vmstate_mpx = {
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+    .name = "cpu/mpx",
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+    .version_id = 1,
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+    .minimum_version_id = 1,
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+    .minimum_version_id_old = 1,
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+    .fields      = (VMStateField[]) {
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+        VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4),
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+        VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU),
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+        VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU),
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+        VMSTATE_UINT64(env.msr_bndcfgs, X86CPU),
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+        VMSTATE_END_OF_LIST()
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+    }
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+};
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+
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 const VMStateDescription vmstate_x86_cpu = {
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     .name = "cpu",
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     .version_id = 12,
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@@ -713,6 +761,9 @@ const VMStateDescription vmstate_x86_cpu = {
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             .vmsd = &vmstate_msr_hyperv_time,
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             .needed = hyperv_time_enable_needed,
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         } , {
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+            .vmsd = &vmstate_mpx,
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+            .needed = mpx_needed,
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+        } , {
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             /* empty */
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         }
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     }
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-- 
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1.8.3.1
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