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Blame SOURCES/kvm-target-i386-Avoid-shifting-left-into-sign-bit.patch

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From ded1f83456d03cef5f99abe18a6c7568b0ecd656 Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Thu, 25 Jun 2015 19:31:28 +0200
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Subject: [PATCH 08/10] target-i386: Avoid shifting left into sign bit
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Message-id: <1435260689-9556-8-git-send-email-ehabkost@redhat.com>
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Patchwork-id: 66504
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O-Subject: [RHEL-7.2 qemu-kvm PATCH 7/8] target-i386: Avoid shifting left into sign bit
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Bugzilla: 1233350
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Bandan Das <bsd@redhat.com>
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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From: Peter Maydell <peter.maydell@linaro.org>
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Add 'U' suffixes where necessary to avoid (1 << 31) which
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shifts left into the sign bit, which is undefined behaviour.
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Add the suffix also for other constants in the same groupings
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even if they don't shift into bit 31, for consistency.
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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(cherry picked from commit 2cd49cbfab0dd294de421893048ab614518fa263)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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 target-i386/cpu.h | 334 +++++++++++++++++++++++++++---------------------------
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 1 file changed, 167 insertions(+), 167 deletions(-)
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diff --git a/target-i386/cpu.h b/target-i386/cpu.h
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index 715ba63..fc1e42e 100644
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--- a/target-i386/cpu.h
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+++ b/target-i386/cpu.h
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@@ -194,35 +194,35 @@
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 #define CR0_PE_SHIFT 0
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 #define CR0_MP_SHIFT 1
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-#define CR0_PE_MASK  (1 << 0)
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-#define CR0_MP_MASK  (1 << 1)
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-#define CR0_EM_MASK  (1 << 2)
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-#define CR0_TS_MASK  (1 << 3)
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-#define CR0_ET_MASK  (1 << 4)
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-#define CR0_NE_MASK  (1 << 5)
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-#define CR0_WP_MASK  (1 << 16)
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-#define CR0_AM_MASK  (1 << 18)
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-#define CR0_PG_MASK  (1 << 31)
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-
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-#define CR4_VME_MASK  (1 << 0)
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-#define CR4_PVI_MASK  (1 << 1)
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-#define CR4_TSD_MASK  (1 << 2)
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-#define CR4_DE_MASK   (1 << 3)
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-#define CR4_PSE_MASK  (1 << 4)
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-#define CR4_PAE_MASK  (1 << 5)
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-#define CR4_MCE_MASK  (1 << 6)
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-#define CR4_PGE_MASK  (1 << 7)
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-#define CR4_PCE_MASK  (1 << 8)
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+#define CR0_PE_MASK  (1U << 0)
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+#define CR0_MP_MASK  (1U << 1)
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+#define CR0_EM_MASK  (1U << 2)
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+#define CR0_TS_MASK  (1U << 3)
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+#define CR0_ET_MASK  (1U << 4)
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+#define CR0_NE_MASK  (1U << 5)
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+#define CR0_WP_MASK  (1U << 16)
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+#define CR0_AM_MASK  (1U << 18)
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+#define CR0_PG_MASK  (1U << 31)
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+
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+#define CR4_VME_MASK  (1U << 0)
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+#define CR4_PVI_MASK  (1U << 1)
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+#define CR4_TSD_MASK  (1U << 2)
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+#define CR4_DE_MASK   (1U << 3)
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+#define CR4_PSE_MASK  (1U << 4)
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+#define CR4_PAE_MASK  (1U << 5)
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+#define CR4_MCE_MASK  (1U << 6)
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+#define CR4_PGE_MASK  (1U << 7)
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+#define CR4_PCE_MASK  (1U << 8)
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 #define CR4_OSFXSR_SHIFT 9
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-#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
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-#define CR4_OSXMMEXCPT_MASK  (1 << 10)
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-#define CR4_VMXE_MASK   (1 << 13)
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-#define CR4_SMXE_MASK   (1 << 14)
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-#define CR4_FSGSBASE_MASK (1 << 16)
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-#define CR4_PCIDE_MASK  (1 << 17)
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-#define CR4_OSXSAVE_MASK (1 << 18)
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-#define CR4_SMEP_MASK   (1 << 20)
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-#define CR4_SMAP_MASK   (1 << 21)
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+#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
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+#define CR4_OSXMMEXCPT_MASK  (1U << 10)
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+#define CR4_VMXE_MASK   (1U << 13)
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+#define CR4_SMXE_MASK   (1U << 14)
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+#define CR4_FSGSBASE_MASK (1U << 16)
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+#define CR4_PCIDE_MASK  (1U << 17)
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+#define CR4_OSXSAVE_MASK (1U << 18)
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+#define CR4_SMEP_MASK   (1U << 20)
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+#define CR4_SMAP_MASK   (1U << 21)
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 #define DR6_BD          (1 << 13)
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 #define DR6_BS          (1 << 14)
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@@ -408,96 +408,96 @@ typedef enum FeatureWord {
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 typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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 /* cpuid_features bits */
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-#define CPUID_FP87 (1 << 0)
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-#define CPUID_VME  (1 << 1)
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-#define CPUID_DE   (1 << 2)
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-#define CPUID_PSE  (1 << 3)
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-#define CPUID_TSC  (1 << 4)
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-#define CPUID_MSR  (1 << 5)
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-#define CPUID_PAE  (1 << 6)
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-#define CPUID_MCE  (1 << 7)
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-#define CPUID_CX8  (1 << 8)
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-#define CPUID_APIC (1 << 9)
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-#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
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-#define CPUID_MTRR (1 << 12)
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-#define CPUID_PGE  (1 << 13)
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-#define CPUID_MCA  (1 << 14)
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-#define CPUID_CMOV (1 << 15)
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-#define CPUID_PAT  (1 << 16)
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-#define CPUID_PSE36   (1 << 17)
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-#define CPUID_PN   (1 << 18)
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-#define CPUID_CLFLUSH (1 << 19)
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-#define CPUID_DTS (1 << 21)
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-#define CPUID_ACPI (1 << 22)
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-#define CPUID_MMX  (1 << 23)
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-#define CPUID_FXSR (1 << 24)
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-#define CPUID_SSE  (1 << 25)
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-#define CPUID_SSE2 (1 << 26)
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-#define CPUID_SS (1 << 27)
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-#define CPUID_HT (1 << 28)
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-#define CPUID_TM (1 << 29)
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-#define CPUID_IA64 (1 << 30)
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-#define CPUID_PBE (1 << 31)
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-
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-#define CPUID_EXT_SSE3     (1 << 0)
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-#define CPUID_EXT_PCLMULQDQ (1 << 1)
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-#define CPUID_EXT_DTES64   (1 << 2)
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-#define CPUID_EXT_MONITOR  (1 << 3)
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-#define CPUID_EXT_DSCPL    (1 << 4)
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-#define CPUID_EXT_VMX      (1 << 5)
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-#define CPUID_EXT_SMX      (1 << 6)
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-#define CPUID_EXT_EST      (1 << 7)
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-#define CPUID_EXT_TM2      (1 << 8)
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-#define CPUID_EXT_SSSE3    (1 << 9)
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-#define CPUID_EXT_CID      (1 << 10)
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-#define CPUID_EXT_FMA      (1 << 12)
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-#define CPUID_EXT_CX16     (1 << 13)
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-#define CPUID_EXT_XTPR     (1 << 14)
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-#define CPUID_EXT_PDCM     (1 << 15)
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-#define CPUID_EXT_PCID     (1 << 17)
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-#define CPUID_EXT_DCA      (1 << 18)
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-#define CPUID_EXT_SSE41    (1 << 19)
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-#define CPUID_EXT_SSE42    (1 << 20)
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-#define CPUID_EXT_X2APIC   (1 << 21)
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-#define CPUID_EXT_MOVBE    (1 << 22)
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-#define CPUID_EXT_POPCNT   (1 << 23)
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-#define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24)
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-#define CPUID_EXT_AES      (1 << 25)
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-#define CPUID_EXT_XSAVE    (1 << 26)
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-#define CPUID_EXT_OSXSAVE  (1 << 27)
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-#define CPUID_EXT_AVX      (1 << 28)
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-#define CPUID_EXT_F16C     (1 << 29)
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-#define CPUID_EXT_RDRAND   (1 << 30)
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-#define CPUID_EXT_HYPERVISOR  (1 << 31)
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-
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-#define CPUID_EXT2_FPU     (1 << 0)
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-#define CPUID_EXT2_VME     (1 << 1)
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-#define CPUID_EXT2_DE      (1 << 2)
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-#define CPUID_EXT2_PSE     (1 << 3)
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-#define CPUID_EXT2_TSC     (1 << 4)
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-#define CPUID_EXT2_MSR     (1 << 5)
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-#define CPUID_EXT2_PAE     (1 << 6)
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-#define CPUID_EXT2_MCE     (1 << 7)
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-#define CPUID_EXT2_CX8     (1 << 8)
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-#define CPUID_EXT2_APIC    (1 << 9)
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-#define CPUID_EXT2_SYSCALL (1 << 11)
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-#define CPUID_EXT2_MTRR    (1 << 12)
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-#define CPUID_EXT2_PGE     (1 << 13)
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-#define CPUID_EXT2_MCA     (1 << 14)
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-#define CPUID_EXT2_CMOV    (1 << 15)
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-#define CPUID_EXT2_PAT     (1 << 16)
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-#define CPUID_EXT2_PSE36   (1 << 17)
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-#define CPUID_EXT2_MP      (1 << 19)
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-#define CPUID_EXT2_NX      (1 << 20)
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-#define CPUID_EXT2_MMXEXT  (1 << 22)
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-#define CPUID_EXT2_MMX     (1 << 23)
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-#define CPUID_EXT2_FXSR    (1 << 24)
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-#define CPUID_EXT2_FFXSR   (1 << 25)
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-#define CPUID_EXT2_PDPE1GB (1 << 26)
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-#define CPUID_EXT2_RDTSCP  (1 << 27)
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-#define CPUID_EXT2_LM      (1 << 29)
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-#define CPUID_EXT2_3DNOWEXT (1 << 30)
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-#define CPUID_EXT2_3DNOW   (1 << 31)
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+#define CPUID_FP87 (1U << 0)
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+#define CPUID_VME  (1U << 1)
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+#define CPUID_DE   (1U << 2)
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+#define CPUID_PSE  (1U << 3)
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+#define CPUID_TSC  (1U << 4)
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+#define CPUID_MSR  (1U << 5)
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+#define CPUID_PAE  (1U << 6)
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+#define CPUID_MCE  (1U << 7)
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+#define CPUID_CX8  (1U << 8)
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+#define CPUID_APIC (1U << 9)
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+#define CPUID_SEP  (1U << 11) /* sysenter/sysexit */
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+#define CPUID_MTRR (1U << 12)
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+#define CPUID_PGE  (1U << 13)
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+#define CPUID_MCA  (1U << 14)
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+#define CPUID_CMOV (1U << 15)
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+#define CPUID_PAT  (1U << 16)
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+#define CPUID_PSE36   (1U << 17)
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+#define CPUID_PN   (1U << 18)
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+#define CPUID_CLFLUSH (1U << 19)
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+#define CPUID_DTS (1U << 21)
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+#define CPUID_ACPI (1U << 22)
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+#define CPUID_MMX  (1U << 23)
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+#define CPUID_FXSR (1U << 24)
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+#define CPUID_SSE  (1U << 25)
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+#define CPUID_SSE2 (1U << 26)
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+#define CPUID_SS (1U << 27)
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+#define CPUID_HT (1U << 28)
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+#define CPUID_TM (1U << 29)
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+#define CPUID_IA64 (1U << 30)
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+#define CPUID_PBE (1U << 31)
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+
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+#define CPUID_EXT_SSE3     (1U << 0)
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+#define CPUID_EXT_PCLMULQDQ (1U << 1)
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+#define CPUID_EXT_DTES64   (1U << 2)
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+#define CPUID_EXT_MONITOR  (1U << 3)
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+#define CPUID_EXT_DSCPL    (1U << 4)
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+#define CPUID_EXT_VMX      (1U << 5)
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+#define CPUID_EXT_SMX      (1U << 6)
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+#define CPUID_EXT_EST      (1U << 7)
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+#define CPUID_EXT_TM2      (1U << 8)
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+#define CPUID_EXT_SSSE3    (1U << 9)
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+#define CPUID_EXT_CID      (1U << 10)
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+#define CPUID_EXT_FMA      (1U << 12)
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+#define CPUID_EXT_CX16     (1U << 13)
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+#define CPUID_EXT_XTPR     (1U << 14)
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+#define CPUID_EXT_PDCM     (1U << 15)
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+#define CPUID_EXT_PCID     (1U << 17)
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+#define CPUID_EXT_DCA      (1U << 18)
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+#define CPUID_EXT_SSE41    (1U << 19)
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+#define CPUID_EXT_SSE42    (1U << 20)
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+#define CPUID_EXT_X2APIC   (1U << 21)
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+#define CPUID_EXT_MOVBE    (1U << 22)
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+#define CPUID_EXT_POPCNT   (1U << 23)
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+#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
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+#define CPUID_EXT_AES      (1U << 25)
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+#define CPUID_EXT_XSAVE    (1U << 26)
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+#define CPUID_EXT_OSXSAVE  (1U << 27)
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+#define CPUID_EXT_AVX      (1U << 28)
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+#define CPUID_EXT_F16C     (1U << 29)
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+#define CPUID_EXT_RDRAND   (1U << 30)
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+#define CPUID_EXT_HYPERVISOR  (1U << 31)
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+
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+#define CPUID_EXT2_FPU     (1U << 0)
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+#define CPUID_EXT2_VME     (1U << 1)
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+#define CPUID_EXT2_DE      (1U << 2)
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+#define CPUID_EXT2_PSE     (1U << 3)
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+#define CPUID_EXT2_TSC     (1U << 4)
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+#define CPUID_EXT2_MSR     (1U << 5)
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+#define CPUID_EXT2_PAE     (1U << 6)
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+#define CPUID_EXT2_MCE     (1U << 7)
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+#define CPUID_EXT2_CX8     (1U << 8)
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+#define CPUID_EXT2_APIC    (1U << 9)
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+#define CPUID_EXT2_SYSCALL (1U << 11)
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+#define CPUID_EXT2_MTRR    (1U << 12)
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+#define CPUID_EXT2_PGE     (1U << 13)
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+#define CPUID_EXT2_MCA     (1U << 14)
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+#define CPUID_EXT2_CMOV    (1U << 15)
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+#define CPUID_EXT2_PAT     (1U << 16)
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+#define CPUID_EXT2_PSE36   (1U << 17)
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+#define CPUID_EXT2_MP      (1U << 19)
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+#define CPUID_EXT2_NX      (1U << 20)
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+#define CPUID_EXT2_MMXEXT  (1U << 22)
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+#define CPUID_EXT2_MMX     (1U << 23)
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+#define CPUID_EXT2_FXSR    (1U << 24)
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+#define CPUID_EXT2_FFXSR   (1U << 25)
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+#define CPUID_EXT2_PDPE1GB (1U << 26)
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+#define CPUID_EXT2_RDTSCP  (1U << 27)
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+#define CPUID_EXT2_LM      (1U << 29)
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+#define CPUID_EXT2_3DNOWEXT (1U << 30)
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+#define CPUID_EXT2_3DNOW   (1U << 31)
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 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
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 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
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@@ -510,53 +510,53 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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                                 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
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                                 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
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-#define CPUID_EXT3_LAHF_LM (1 << 0)
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-#define CPUID_EXT3_CMP_LEG (1 << 1)
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-#define CPUID_EXT3_SVM     (1 << 2)
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-#define CPUID_EXT3_EXTAPIC (1 << 3)
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-#define CPUID_EXT3_CR8LEG  (1 << 4)
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-#define CPUID_EXT3_ABM     (1 << 5)
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-#define CPUID_EXT3_SSE4A   (1 << 6)
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-#define CPUID_EXT3_MISALIGNSSE (1 << 7)
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-#define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
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-#define CPUID_EXT3_OSVW    (1 << 9)
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-#define CPUID_EXT3_IBS     (1 << 10)
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-#define CPUID_EXT3_XOP     (1 << 11)
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-#define CPUID_EXT3_SKINIT  (1 << 12)
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-#define CPUID_EXT3_WDT     (1 << 13)
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-#define CPUID_EXT3_LWP     (1 << 15)
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-#define CPUID_EXT3_FMA4    (1 << 16)
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-#define CPUID_EXT3_TCE     (1 << 17)
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-#define CPUID_EXT3_NODEID  (1 << 19)
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-#define CPUID_EXT3_TBM     (1 << 21)
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-#define CPUID_EXT3_TOPOEXT (1 << 22)
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-#define CPUID_EXT3_PERFCORE (1 << 23)
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-#define CPUID_EXT3_PERFNB  (1 << 24)
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-
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-#define CPUID_SVM_NPT          (1 << 0)
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-#define CPUID_SVM_LBRV         (1 << 1)
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-#define CPUID_SVM_SVMLOCK      (1 << 2)
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-#define CPUID_SVM_NRIPSAVE     (1 << 3)
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-#define CPUID_SVM_TSCSCALE     (1 << 4)
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-#define CPUID_SVM_VMCBCLEAN    (1 << 5)
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-#define CPUID_SVM_FLUSHASID    (1 << 6)
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-#define CPUID_SVM_DECODEASSIST (1 << 7)
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-#define CPUID_SVM_PAUSEFILTER  (1 << 10)
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-#define CPUID_SVM_PFTHRESHOLD  (1 << 12)
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-
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-#define CPUID_7_0_EBX_FSGSBASE (1 << 0)
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-#define CPUID_7_0_EBX_BMI1     (1 << 3)
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-#define CPUID_7_0_EBX_HLE      (1 << 4)
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-#define CPUID_7_0_EBX_AVX2     (1 << 5)
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-#define CPUID_7_0_EBX_SMEP     (1 << 7)
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-#define CPUID_7_0_EBX_BMI2     (1 << 8)
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-#define CPUID_7_0_EBX_ERMS     (1 << 9)
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-#define CPUID_7_0_EBX_INVPCID  (1 << 10)
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-#define CPUID_7_0_EBX_RTM      (1 << 11)
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-#define CPUID_7_0_EBX_MPX      (1 << 14)
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-#define CPUID_7_0_EBX_RDSEED   (1 << 18)
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-#define CPUID_7_0_EBX_ADX      (1 << 19)
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-#define CPUID_7_0_EBX_SMAP     (1 << 20)
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+#define CPUID_EXT3_LAHF_LM (1U << 0)
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+#define CPUID_EXT3_CMP_LEG (1U << 1)
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+#define CPUID_EXT3_SVM     (1U << 2)
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+#define CPUID_EXT3_EXTAPIC (1U << 3)
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+#define CPUID_EXT3_CR8LEG  (1U << 4)
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+#define CPUID_EXT3_ABM     (1U << 5)
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+#define CPUID_EXT3_SSE4A   (1U << 6)
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+#define CPUID_EXT3_MISALIGNSSE (1U << 7)
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+#define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
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+#define CPUID_EXT3_OSVW    (1U << 9)
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+#define CPUID_EXT3_IBS     (1U << 10)
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+#define CPUID_EXT3_XOP     (1U << 11)
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+#define CPUID_EXT3_SKINIT  (1U << 12)
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+#define CPUID_EXT3_WDT     (1U << 13)
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+#define CPUID_EXT3_LWP     (1U << 15)
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+#define CPUID_EXT3_FMA4    (1U << 16)
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+#define CPUID_EXT3_TCE     (1U << 17)
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+#define CPUID_EXT3_NODEID  (1U << 19)
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+#define CPUID_EXT3_TBM     (1U << 21)
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+#define CPUID_EXT3_TOPOEXT (1U << 22)
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+#define CPUID_EXT3_PERFCORE (1U << 23)
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+#define CPUID_EXT3_PERFNB  (1U << 24)
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+
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+#define CPUID_SVM_NPT          (1U << 0)
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+#define CPUID_SVM_LBRV         (1U << 1)
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+#define CPUID_SVM_SVMLOCK      (1U << 2)
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+#define CPUID_SVM_NRIPSAVE     (1U << 3)
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+#define CPUID_SVM_TSCSCALE     (1U << 4)
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+#define CPUID_SVM_VMCBCLEAN    (1U << 5)
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+#define CPUID_SVM_FLUSHASID    (1U << 6)
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+#define CPUID_SVM_DECODEASSIST (1U << 7)
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+#define CPUID_SVM_PAUSEFILTER  (1U << 10)
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+#define CPUID_SVM_PFTHRESHOLD  (1U << 12)
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+
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+#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
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+#define CPUID_7_0_EBX_BMI1     (1U << 3)
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+#define CPUID_7_0_EBX_HLE      (1U << 4)
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+#define CPUID_7_0_EBX_AVX2     (1U << 5)
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+#define CPUID_7_0_EBX_SMEP     (1U << 7)
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+#define CPUID_7_0_EBX_BMI2     (1U << 8)
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+#define CPUID_7_0_EBX_ERMS     (1U << 9)
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+#define CPUID_7_0_EBX_INVPCID  (1U << 10)
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+#define CPUID_7_0_EBX_RTM      (1U << 11)
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+#define CPUID_7_0_EBX_MPX      (1U << 14)
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+#define CPUID_7_0_EBX_RDSEED   (1U << 18)
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+#define CPUID_7_0_EBX_ADX      (1U << 19)
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+#define CPUID_7_0_EBX_SMAP     (1U << 20)
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 #define CPUID_VENDOR_SZ      12
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@@ -572,8 +572,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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 #define CPUID_VENDOR_VIA   "CentaurHauls"
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-#define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
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-#define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
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+#define CPUID_MWAIT_IBE     (1U << 1) /* Interrupts can exit capability */
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+#define CPUID_MWAIT_EMX     (1U << 0) /* enumeration supported */
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 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
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 #define HYPERV_SPINLOCK_NEVER_RETRY             0xFFFFFFFF
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-- 
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1.8.3.1
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