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From 1b37b298fc1f0d69e24229191e4bbe741e4d96ab Mon Sep 17 00:00:00 2001
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From: Fam Zheng <famz@redhat.com>
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Date: Thu, 18 May 2017 09:21:25 +0200
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Subject: [PATCH 12/18] serial: clean up THRE/TEMT handling
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RH-Author: Fam Zheng <famz@redhat.com>
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Message-id: <20170518092131.16571-13-famz@redhat.com>
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Patchwork-id: 75303
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O-Subject: [RHEL-7.4 qemu-kvm PATCH v3 12/18] serial: clean up THRE/TEMT handling
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Bugzilla: 1451470
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Stefan Hajnoczi <stefanha@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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From: Paolo Bonzini <pbonzini@redhat.com>
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- assert TEMT is cleared before sending a character; we'll get one from
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TSR if tsr_retry > 0, from the FIFO or THR otherwise
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- assert THRE cleared and FIFO not empty (if enabled) before fetching a
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character to send.  This effectively reverts dffacd46, but the check
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makes no sense and commit f702e62 (serial: change retry logic to avoid
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concurrency, 2014-07-11) must have made it unnecessary.  The commit
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message for f702e62 talks about multiple calls to qemu_chr_fe_add_watch
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triggering s->tsr_retry >= MAX_XMIT_RETRY, but other failures were
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possible.  For example, if you have multiple calls, the subsequent ones
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will see s->tsr_retry == 0 and will find THRE and/or TEMT on entry.
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- for clarity, raise THRI immediately after the code sets THRE
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- check THRE to see if another character has to be sent.  This makes
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the assertions more obvious and also means TEMT has to be set as soon as
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the loop ends.  It makes the loop send both TSR and THR if flow-control
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happens in non-FIFO mode.  Previously, THR would be lost.
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- clear TEMT together with THRE even in the non-FIFO case
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The last two items are bugfixes, but they were just found by inspection
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and do not squash known bugs.
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Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 0d931d706266d6ada3bf22d3afca1afdc8d12fa9)
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Signed-off-by: Fam Zheng <famz@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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Conflicts:
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	hw/char/serial.c
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Contextual conflict because upstream has the new timer API
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qemu_clock_get_ns, but downstream still uses qemu_get_clock_ns.
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---
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 hw/char/serial.c | 26 ++++++++++++--------------
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 1 file changed, 12 insertions(+), 14 deletions(-)
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diff --git a/hw/char/serial.c b/hw/char/serial.c
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index 15c628f..c2be4bd 100644
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--- a/hw/char/serial.c
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+++ b/hw/char/serial.c
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@@ -224,21 +224,23 @@ static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque)
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     SerialState *s = opaque;
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     do {
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+        assert(!(s->lsr & UART_LSR_TEMT));
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         if (s->tsr_retry <= 0) {
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+            assert(!(s->lsr & UART_LSR_THRE));
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+
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             if (s->fcr & UART_FCR_FE) {
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-                if (fifo8_is_empty(&s->xmit_fifo)) {
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-                    return FALSE;
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-                }
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+                assert(!fifo8_is_empty(&s->xmit_fifo));
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                 s->tsr = fifo8_pop(&s->xmit_fifo);
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                 if (!s->xmit_fifo.num) {
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                     s->lsr |= UART_LSR_THRE;
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                 }
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-            } else if ((s->lsr & UART_LSR_THRE)) {
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-                return FALSE;
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             } else {
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                 s->tsr = s->thr;
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                 s->lsr |= UART_LSR_THRE;
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-                s->lsr &= ~UART_LSR_TEMT;
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+            }
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+            if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) {
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+                s->thr_ipending = 1;
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+                serial_update_irq(s);
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             }
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         }
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@@ -256,17 +258,13 @@ static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque)
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         } else {
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             s->tsr_retry = 0;
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         }
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+
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         /* Transmit another byte if it is already available. It is only
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            possible when FIFO is enabled and not empty. */
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-    } while ((s->fcr & UART_FCR_FE) && !fifo8_is_empty(&s->xmit_fifo));
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+    } while (!(s->lsr & UART_LSR_THRE));
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     s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
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-
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-    if (s->lsr & UART_LSR_THRE) {
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-        s->lsr |= UART_LSR_TEMT;
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-        s->thr_ipending = 1;
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-        serial_update_irq(s);
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-    }
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+    s->lsr |= UART_LSR_TEMT;
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     return FALSE;
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 }
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@@ -293,10 +291,10 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
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                     fifo8_pop(&s->xmit_fifo);
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                 }
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                 fifo8_push(&s->xmit_fifo, s->thr);
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-                s->lsr &= ~UART_LSR_TEMT;
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             }
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             s->thr_ipending = 0;
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             s->lsr &= ~UART_LSR_THRE;
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+            s->lsr &= ~UART_LSR_TEMT;
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             serial_update_irq(s);
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             if (s->tsr_retry <= 0) {
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                 serial_xmit(NULL, G_IO_OUT, s);
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-- 
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1.8.3.1
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