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From 1cf1fcaf322e07354e830f2562db856ecbb1bf4c Mon Sep 17 00:00:00 2001
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Message-Id: <1cf1fcaf322e07354e830f2562db856ecbb1bf4c.1387298827.git.minovotn@redhat.com>
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In-Reply-To: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
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References: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
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From: "Michael S. Tsirkin" <mst@redhat.com>
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Date: Tue, 17 Dec 2013 15:17:45 +0100
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Subject: [PATCH 22/56] pc: fix regression for 64 bit PCI memory
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RH-Author: Michael S. Tsirkin <mst@redhat.com>
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Message-id: <1387293161-4085-23-git-send-email-mst@redhat.com>
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Patchwork-id: 56328
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O-Subject: [PATCH qemu-kvm RHEL7.0 v2 22/57] pc: fix regression for 64 bit PCI memory
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Bugzilla: 1034876
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Marcel Apfelbaum <marcel.a@redhat.com>
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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commit 398489018183d613306ab022653552247d93919f
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    pc: limit 64 bit hole to 2G by default
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introduced a way for management to control
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the window allocated to the 64 bit PCI hole.
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This is useful, but existing management tools do not know how to set
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this property.  As a result, e.g. specifying a large ivshmem device with
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size > 4G is broken by default.  For example this configuration no
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longer works:
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-device ivshmem,size=4294967296,chardev=cfoo
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-chardev socket,path=/tmp/sock,id=cfoo,server,nowait
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Fix this by detecting that hole size was not specified
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and defaulting to the backwards-compatible value of 1 << 62.
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Cc: qemu-stable@nongnu.org
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Cc: Igor Mammedov <imammedo@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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(cherry picked from commit 1466cef32dd5e7ef3c6477e96d85d92302ad02e3)
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Conflicts:
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	hw/pci-host/piix.c
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	hw/pci-host/q35.c
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---
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 include/hw/i386/pc.h | 11 ++++++++++-
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 hw/pci-host/piix.c   |  9 ++++++---
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 hw/pci-host/q35.c    |  8 +++++---
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 3 files changed, 21 insertions(+), 7 deletions(-)
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Signed-off-by: Michal Novotny <minovotn@redhat.com>
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---
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 hw/pci-host/piix.c   |  9 ++++++---
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 hw/pci-host/q35.c    |  8 +++++---
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 include/hw/i386/pc.h | 11 ++++++++++-
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 3 files changed, 21 insertions(+), 7 deletions(-)
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diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
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index 0c26835..6502d1c 100644
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--- a/hw/pci-host/piix.c
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+++ b/hw/pci-host/piix.c
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@@ -319,6 +319,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
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     PCII440FXState *f;
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     unsigned i;
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     I440FXState *i440fx;
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+    uint64_t pci_hole64_size;
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     dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE);
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     s = PCI_HOST_BRIDGE(dev);
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@@ -350,13 +351,15 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
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                              pci_hole_start, pci_hole_size);
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     memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
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+    pci_hole64_size = pci_host_get_hole64_size(i440fx->pci_hole64_size);
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+
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     pc_init_pci64_hole(&i440fx->pci_info, 0x100000000ULL + above_4g_mem_size,
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-                       i440fx->pci_hole64_size);
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+                       pci_hole64_size);
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     memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
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                              f->pci_address_space,
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                              i440fx->pci_info.w64.begin,
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-                             i440fx->pci_hole64_size);
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-    if (i440fx->pci_hole64_size) {
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+                             pci_hole64_size);
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+    if (pci_hole64_size) {
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         memory_region_add_subregion(f->system_memory,
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                                     i440fx->pci_info.w64.begin,
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                                     &f->pci_hole_64bit);
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diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
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index 943e55f..05779b8 100644
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--- a/hw/pci-host/q35.c
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+++ b/hw/pci-host/q35.c
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@@ -325,6 +325,7 @@ static int mch_init(PCIDevice *d)
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 {
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     int i;
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     MCHPCIState *mch = MCH_PCI_DEVICE(d);
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+    uint64_t pci_hole64_size;
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     /* setup pci memory regions */
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     memory_region_init_alias(&mch->pci_hole, "pci-hole",
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@@ -334,13 +335,14 @@ static int mch_init(PCIDevice *d)
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     memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size,
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                                 &mch->pci_hole);
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+    pci_hole64_size = pci_host_get_hole64_size(mch->pci_hole64_size);
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     pc_init_pci64_hole(&mch->pci_info, 0x100000000ULL + mch->above_4g_mem_size,
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-                       mch->pci_hole64_size);
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+                       pci_hole64_size);
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     memory_region_init_alias(&mch->pci_hole_64bit, "pci-hole64",
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                              mch->pci_address_space,
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                              mch->pci_info.w64.begin,
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-                             mch->pci_hole64_size);
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-    if (mch->pci_hole64_size) {
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+                             pci_hole64_size);
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+    if (pci_hole64_size) {
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         memory_region_add_subregion(mch->system_memory,
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                                     mch->pci_info.w64.begin,
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                                     &mch->pci_hole_64bit);
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diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
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index fe21bc3..abaaf93 100644
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--- a/include/hw/i386/pc.h
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+++ b/include/hw/i386/pc.h
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@@ -105,7 +105,16 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
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 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
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 #define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
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 #define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
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-#define DEFAULT_PCI_HOLE64_SIZE (1ULL << 31)
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+#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
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+
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+static inline uint64_t pci_host_get_hole64_size(uint64_t pci_hole64_size)
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+{
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+    if (pci_hole64_size == DEFAULT_PCI_HOLE64_SIZE) {
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+        return 1ULL << 62;
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+    } else {
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+        return pci_hole64_size;
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+    }
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+}
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 void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
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                         uint64_t pci_hole64_size);
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-- 
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1.7.11.7
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