cryptospore / rpms / qemu-kvm

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From 7bb09ff3360af16599cc2cae834f676a20cdfa88 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Wed, 6 Nov 2013 08:27:29 +0100
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Subject: [PATCH 02/29] kvm: migrate vPMU state
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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Message-id: <1379955972-3080-3-git-send-email-pbonzini@redhat.com>
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Patchwork-id: 54487
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O-Subject: [RHEL 7.0 qemu-kvm PATCH 2/2] kvm: migrate vPMU state
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Bugzilla: 928867
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RH-Acked-by: Juan Quintela <quintela@redhat.com>
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RH-Acked-by: Marcelo Tosatti <mtosatti@redhat.com>
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RH-Acked-by: Bandan Das <bsd@redhat.com>
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Reviewed-by: Gleb Natapov <gnatapov@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry-picked from commit 0d89436786b02a9e7d561c4d7dc4982e4a2739db)
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Conflicts:
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	target-i386/machine.c
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        [missing 0779cae, Initialize IA32_FEATURE_CONTROL MSR in reset and migration, 2013-07-07]
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Signed-of-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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 target-i386/cpu.h     |   23 ++++++++++++
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 target-i386/kvm.c     |   93 ++++++++++++++++++++++++++++++++++++++++++++++---
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 target-i386/machine.c |   44 +++++++++++++++++++++++
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 3 files changed, 155 insertions(+), 5 deletions(-)
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diff --git a/target-i386/cpu.h b/target-i386/cpu.h
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index 74c7899..6aebc80 100644
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--- a/target-i386/cpu.h
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+++ b/target-i386/cpu.h
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@@ -304,6 +304,8 @@
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 #define MSR_TSC_ADJUST                  0x0000003b
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 #define MSR_IA32_TSCDEADLINE            0x6e0
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+#define MSR_P6_PERFCTR0                 0xc1
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+
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 #define MSR_MTRRcap                     0xfe
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 #define MSR_MTRRcap_VCNT                8
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 #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
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@@ -317,6 +319,8 @@
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 #define MSR_MCG_STATUS                  0x17a
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 #define MSR_MCG_CTL                     0x17b
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+#define MSR_P6_EVNTSEL0                 0x186
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+
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 #define MSR_IA32_PERF_STATUS            0x198
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 #define MSR_IA32_MISC_ENABLE            0x1a0
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@@ -342,6 +346,14 @@
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 #define MSR_MTRRdefType                 0x2ff
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+#define MSR_CORE_PERF_FIXED_CTR0        0x309
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+#define MSR_CORE_PERF_FIXED_CTR1        0x30a
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+#define MSR_CORE_PERF_FIXED_CTR2        0x30b
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+#define MSR_CORE_PERF_FIXED_CTR_CTRL    0x38d
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+#define MSR_CORE_PERF_GLOBAL_STATUS     0x38e
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+#define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
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+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
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+
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 #define MSR_MC0_CTL                     0x400
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 #define MSR_MC0_STATUS                  0x401
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 #define MSR_MC0_ADDR                    0x402
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@@ -720,6 +732,9 @@ typedef struct {
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 #define CPU_NB_REGS CPU_NB_REGS32
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 #endif
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+#define MAX_FIXED_COUNTERS 3
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+#define MAX_GP_COUNTERS    (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
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+
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 #define NB_MMU_MODES 3
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 typedef enum TPRAccess {
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@@ -814,6 +829,14 @@ typedef struct CPUX86State {
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     uint64_t mcg_status;
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     uint64_t msr_ia32_misc_enable;
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+    uint64_t msr_fixed_ctr_ctrl;
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+    uint64_t msr_global_ctrl;
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+    uint64_t msr_global_status;
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+    uint64_t msr_global_ovf_ctrl;
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+    uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
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+    uint64_t msr_gp_counters[MAX_GP_COUNTERS];
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+    uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
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+
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     /* exception/interrupt handling */
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     int error_code;
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     int exception_is_int;
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diff --git a/target-i386/kvm.c b/target-i386/kvm.c
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index c5a9416..4b470e4 100644
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--- a/target-i386/kvm.c
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+++ b/target-i386/kvm.c
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@@ -71,6 +71,9 @@ static bool has_msr_misc_enable;
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 static bool has_msr_kvm_steal_time;
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 static int lm_capable_kernel;
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+static bool has_msr_architectural_pmu;
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+static uint32_t num_architectural_pmu_counters;
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+
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 bool kvm_allows_irq0_override(void)
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 {
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     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
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@@ -579,6 +582,25 @@ int kvm_arch_init_vcpu(CPUState *cs)
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             break;
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         }
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     }
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+
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+    if (limit >= 0x0a) {
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+        uint32_t ver;
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+
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+        cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
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+        if ((ver & 0xff) > 0) {
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+            has_msr_architectural_pmu = true;
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+            num_architectural_pmu_counters = (ver & 0xff00) >> 8;
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+
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+            /* Shouldn't be more than 32, since that's the number of bits
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+             * available in EBX to tell us _which_ counters are available.
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+             * Play it safe.
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+             */
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+            if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
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+                num_architectural_pmu_counters = MAX_GP_COUNTERS;
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+            }
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+        }
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+    }
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+
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     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
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     for (i = 0x80000000; i <= limit; i++) {
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@@ -1070,7 +1092,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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         struct kvm_msr_entry entries[100];
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     } msr_data;
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     struct kvm_msr_entry *msrs = msr_data.entries;
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-    int n = 0;
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+    int n = 0, i;
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     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
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     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
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@@ -1109,9 +1131,8 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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         }
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     }
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     /*
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-     * The following paravirtual MSRs have side effects on the guest or are
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-     * too heavy for normal writeback. Limit them to reset or full state
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-     * updates.
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+     * The following MSRs have side effects on the guest or are too heavy
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+     * for normal writeback. Limit them to reset or full state updates.
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      */
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     if (level >= KVM_PUT_RESET_STATE) {
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         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
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@@ -1129,6 +1150,33 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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             kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
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                               env->steal_time_msr);
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         }
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+        if (has_msr_architectural_pmu) {
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+            /* Stop the counter.  */
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+            kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
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+            kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
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+
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+            /* Set the counter values.  */
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+            for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
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+                kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
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+                                  env->msr_fixed_counters[i]);
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+            }
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+            for (i = 0; i < num_architectural_pmu_counters; i++) {
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+                kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
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+                                  env->msr_gp_counters[i]);
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+                kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
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+                                  env->msr_gp_evtsel[i]);
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+            }
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+            kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
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+                              env->msr_global_status);
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+            kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
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+                              env->msr_global_ovf_ctrl);
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+
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+            /* Now start the PMU.  */
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+            kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
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+                              env->msr_fixed_ctr_ctrl);
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+            kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
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+                              env->msr_global_ctrl);
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+        }
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         if (hyperv_hypercall_available()) {
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             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
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             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
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@@ -1385,6 +1433,19 @@ static int kvm_get_msrs(X86CPU *cpu)
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     if (has_msr_kvm_steal_time) {
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         msrs[n++].index = MSR_KVM_STEAL_TIME;
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     }
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+    if (has_msr_architectural_pmu) {
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+        msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
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+        msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
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+        msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
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+        msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
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+        for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
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+            msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
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+        }
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+        for (i = 0; i < num_architectural_pmu_counters; i++) {
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+            msrs[n++].index = MSR_P6_PERFCTR0 + i;
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+            msrs[n++].index = MSR_P6_EVNTSEL0 + i;
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+        }
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+    }
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     if (env->mcg_cap) {
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         msrs[n++].index = MSR_MCG_STATUS;
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@@ -1401,7 +1462,8 @@ static int kvm_get_msrs(X86CPU *cpu)
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     }
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     for (i = 0; i < ret; i++) {
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-        switch (msrs[i].index) {
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+        uint32_t index = msrs[i].index;
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+        switch (index) {
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         case MSR_IA32_SYSENTER_CS:
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             env->sysenter_cs = msrs[i].data;
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             break;
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@@ -1473,6 +1535,27 @@ static int kvm_get_msrs(X86CPU *cpu)
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         case MSR_KVM_STEAL_TIME:
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             env->steal_time_msr = msrs[i].data;
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             break;
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+        case MSR_CORE_PERF_FIXED_CTR_CTRL:
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+            env->msr_fixed_ctr_ctrl = msrs[i].data;
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+            break;
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+        case MSR_CORE_PERF_GLOBAL_CTRL:
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+            env->msr_global_ctrl = msrs[i].data;
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+            break;
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+        case MSR_CORE_PERF_GLOBAL_STATUS:
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+            env->msr_global_status = msrs[i].data;
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+            break;
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+        case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
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+            env->msr_global_ovf_ctrl = msrs[i].data;
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+            break;
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+        case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
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+            env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
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+            break;
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+        case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
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+            env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
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+            break;
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+        case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
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+            env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
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+            break;
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         }
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     }
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diff --git a/target-i386/machine.c b/target-i386/machine.c
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index 4f30347..08b4ed3 100644
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--- a/target-i386/machine.c
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+++ b/target-i386/machine.c
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@@ -465,6 +465,47 @@ static const VMStateDescription vmstate_xsave ={
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     }
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 };
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+static bool pmu_enable_needed(void *opaque)
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+{
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+    X86CPU *cpu = opaque;
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+    CPUX86State *env = &cpu->env;
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+    int i;
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+
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+    if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
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+        env->msr_global_status || env->msr_global_ovf_ctrl) {
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+        return true;
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+    }
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+    for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
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+        if (env->msr_fixed_counters[i]) {
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+            return true;
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+        }
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+    }
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+    for (i = 0; i < MAX_GP_COUNTERS; i++) {
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+        if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) {
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+            return true;
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+        }
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+    }
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+
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+    return false;
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+}
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+
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+static const VMStateDescription vmstate_msr_architectural_pmu = {
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+    .name = "cpu/msr_architectural_pmu",
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+    .version_id = 1,
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+    .minimum_version_id = 1,
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+    .minimum_version_id_old = 1,
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+    .fields      = (VMStateField []) {
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+        VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU),
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+        VMSTATE_UINT64(env.msr_global_ctrl, X86CPU),
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+        VMSTATE_UINT64(env.msr_global_status, X86CPU),
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+        VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU),
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+        VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS),
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+        VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS),
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+        VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS),
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+        VMSTATE_END_OF_LIST()
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+    }
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+};
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+
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 const VMStateDescription vmstate_x86_cpu = {
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     .name = "cpu",
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     .version_id = 12,
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@@ -594,6 +635,9 @@ const VMStateDescription vmstate_x86_cpu = {
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             .vmsd = &vmstate_xsave,
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             .needed = vmstate_xsave_needed,
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         }, {
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+            .vmsd = &vmstate_msr_architectural_pmu,
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+            .needed = pmu_enable_needed,
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+        }, {
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             /* empty */
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         }
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     }
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-- 
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1.7.1
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