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Blame SOURCES/kvm-intel_iommu-better-handling-of-dmar-state-switch.patch

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From 467b5e3127faf168fba6ce61a602f82d34a699c7 Mon Sep 17 00:00:00 2001
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From: Peter Xu <peterx@redhat.com>
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Date: Thu, 8 Nov 2018 06:29:36 +0000
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Subject: [PATCH 08/35] intel_iommu: better handling of dmar state switch
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RH-Author: Peter Xu <peterx@redhat.com>
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Message-id: <20181108062938.21143-6-peterx@redhat.com>
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Patchwork-id: 82964
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O-Subject: [RHEL-8 qemu-kvm PATCH 5/7] intel_iommu: better handling of dmar state switch
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Bugzilla: 1625173
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RH-Acked-by: Auger Eric <eric.auger@redhat.com>
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RH-Acked-by: Michael S. Tsirkin <mst@redhat.com>
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RH-Acked-by: Laurent Vivier <lvivier@redhat.com>
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Bugzilla: 1625173
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QEMU is not handling the global DMAR switch well, especially when from
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"on" to "off".
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Let's first take the example of system reset.
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Assuming that a guest has IOMMU enabled.  When it reboots, we will drop
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all the existing DMAR mappings to handle the system reset, however we'll
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still keep the existing memory layouts which has the IOMMU memory region
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enabled.  So after the reboot and before the kernel reloads again, there
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will be no mapping at all for the host device.  That's problematic since
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any software (for example, SeaBIOS) that runs earlier than the kernel
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after the reboot will assume the IOMMU is disabled, so any DMA from the
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software will fail.
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For example, a guest that boots on an assigned NVMe device might fail to
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find the boot device after a system reboot/reset and we'll be able to
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observe SeaBIOS errors if we capture the debugging log:
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  WARNING - Timeout at nvme_wait:144!
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Meanwhile, we should see DMAR errors on the host of that NVMe device.
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It's the DMA fault that caused a NVMe driver timeout.
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The correct fix should be that we do proper switching of device DMA
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address spaces when system resets, which will setup correct memory
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regions and notify the backend of the devices.  This might not affect
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much on non-assigned devices since QEMU VT-d emulation will assume a
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default passthrough mapping if DMAR is not enabled in the GCMD
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register (please refer to vtd_iommu_translate).  However that's required
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for an assigned devices, since that'll rebuild the correct GPA to HPA
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mapping that is needed for any DMA operation during guest bootstrap.
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Besides the system reset, we have some other places that might change
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the global DMAR status and we'd better do the same thing there.  For
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example, when we change the state of GCMD register, or the DMAR root
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pointer.  Do the same refresh for all these places.  For these two
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places we'll also need to explicitly invalidate the context entry cache
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and iotlb cache.
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Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1625173
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CC: QEMU Stable <qemu-stable@nongnu.org>
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Reported-by: Cong Li <coli@redhat.com>
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Signed-off-by: Peter Xu <peterx@redhat.com>
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--
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v2:
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- do the same for GCMD write, or root pointer update [Alex]
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- test is carried out by me this time, by observing the
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  vtd_switch_address_space tracepoint after system reboot
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v3:
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- rewrite commit message as suggested by Alex
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Signed-off-by: Peter Xu <peterx@redhat.com>
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Reviewed-by: Eric Auger <eric.auger@redhat.com>
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Reviewed-by: Jason Wang <jasowang@redhat.com>
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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(cherry picked from commit 2cc9ddccebcaa48b3debfc279a83761fcbb7616c)
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Signed-off-by: Peter Xu <peterx@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 hw/i386/intel_iommu.c | 21 ++++++++++++++-------
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 1 file changed, 14 insertions(+), 7 deletions(-)
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diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
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index 48d0ba3..a6e87a9 100644
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--- a/hw/i386/intel_iommu.c
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+++ b/hw/i386/intel_iommu.c
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@@ -37,6 +37,8 @@
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 #include "kvm_i386.h"
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 #include "trace.h"
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+static void vtd_address_space_refresh_all(IntelIOMMUState *s);
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+
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 static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val,
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                             uint64_t wmask, uint64_t w1cmask)
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 {
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@@ -1436,7 +1438,7 @@ static void vtd_context_global_invalidate(IntelIOMMUState *s)
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         vtd_reset_context_cache_locked(s);
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     }
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     vtd_iommu_unlock(s);
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-    vtd_switch_address_space_all(s);
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+    vtd_address_space_refresh_all(s);
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     /*
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      * From VT-d spec 6.5.2.1, a global context entry invalidation
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      * should be followed by a IOTLB global invalidation, so we should
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@@ -1727,6 +1729,8 @@ static void vtd_handle_gcmd_srtp(IntelIOMMUState *s)
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     vtd_root_table_setup(s);
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     /* Ok - report back to driver */
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     vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS);
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+    vtd_reset_caches(s);
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+    vtd_address_space_refresh_all(s);
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 }
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 /* Set Interrupt Remap Table Pointer */
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@@ -1759,7 +1763,8 @@ static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en)
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         vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0);
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     }
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-    vtd_switch_address_space_all(s);
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+    vtd_reset_caches(s);
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+    vtd_address_space_refresh_all(s);
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 }
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 /* Handle Interrupt Remap Enable/Disable */
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@@ -3059,6 +3064,12 @@ static void vtd_address_space_unmap_all(IntelIOMMUState *s)
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     }
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 }
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+static void vtd_address_space_refresh_all(IntelIOMMUState *s)
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+{
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+    vtd_address_space_unmap_all(s);
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+    vtd_switch_address_space_all(s);
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+}
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+
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 static int vtd_replay_hook(IOMMUTLBEntry *entry, void *private)
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 {
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     memory_region_notify_one((IOMMUNotifier *)private, entry);
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@@ -3231,11 +3242,7 @@ static void vtd_reset(DeviceState *dev)
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     IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
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     vtd_init(s);
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-
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-    /*
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-     * When device reset, throw away all mappings and external caches
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-     */
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-    vtd_address_space_unmap_all(s);
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+    vtd_address_space_refresh_all(s);
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 }
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 static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
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-- 
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1.8.3.1
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