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Blame SOURCES/kvm-i386-Populate-AMD-Processor-Cache-Information-for-cp.patch

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From 9308fcbb870779d4d52f0497dbf68d2651b8895b Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Thu, 26 Jul 2018 17:18:59 +0100
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Subject: [PATCH 09/14] i386: Populate AMD Processor Cache Information for
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 cpuid 0x8000001D
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <20180726171904.27418-7-ehabkost@redhat.com>
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Patchwork-id: 81529
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O-Subject: [qemu-kvm RHEL8/virt212 PATCH v2 06/11] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D
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Bugzilla: 1597739
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Laurent Vivier <lvivier@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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From: Babu Moger <babu.moger@amd.com>
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Add information for cpuid 0x8000001D leaf. Populate cache topology information
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for different cache types (Data Cache, Instruction Cache, L2 and L3) supported
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by 0x8000001D leaf. Please refer to the Processor Programming Reference (PPR)
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for AMD Family 17h Model for more details.
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Signed-off-by: Babu Moger <babu.moger@amd.com>
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Message-Id: <1527176614-26271-3-git-send-email-babu.moger@amd.com>
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Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit 8f4202fb1080f86958782b1fca0bf0279f67d136)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 target/i386/cpu.c | 117 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
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 target/i386/kvm.c |  29 ++++++++++++--
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 2 files changed, 143 insertions(+), 3 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index f98a964..d2474d7 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -337,6 +337,99 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
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 }
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 /*
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+ * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
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+ * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
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+ * Define the constants to build the cpu topology. Right now, TOPOEXT
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+ * feature is enabled only on EPYC. So, these constants are based on
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+ * EPYC supported configurations. We may need to handle the cases if
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+ * these values change in future.
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+ */
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+/* Maximum core complexes in a node */
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+#define MAX_CCX 2
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+/* Maximum cores in a core complex */
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+#define MAX_CORES_IN_CCX 4
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+/* Maximum cores in a node */
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+#define MAX_CORES_IN_NODE 8
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+/* Maximum nodes in a socket */
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+#define MAX_NODES_PER_SOCKET 4
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+
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+/*
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+ * Figure out the number of nodes required to build this config.
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+ * Max cores in a node is 8
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+ */
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+static int nodes_in_socket(int nr_cores)
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+{
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+    int nodes;
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+
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+    nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
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+
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+   /* Hardware does not support config with 3 nodes, return 4 in that case */
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+    return (nodes == 3) ? 4 : nodes;
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+}
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+
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+/*
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+ * Decide the number of cores in a core complex with the given nr_cores using
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+ * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
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+ * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
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+ * L3 cache is shared across all cores in a core complex. So, this will also
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+ * tell us how many cores are sharing the L3 cache.
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+ */
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+static int cores_in_core_complex(int nr_cores)
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+{
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+    int nodes;
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+
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+    /* Check if we can fit all the cores in one core complex */
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+    if (nr_cores <= MAX_CORES_IN_CCX) {
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+        return nr_cores;
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+    }
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+    /* Get the number of nodes required to build this config */
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+    nodes = nodes_in_socket(nr_cores);
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+
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+    /*
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+     * Divide the cores accros all the core complexes
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+     * Return rounded up value
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+     */
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+    return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
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+}
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+
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+/* Encode cache info for CPUID[8000001D] */
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+static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
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+                                uint32_t *eax, uint32_t *ebx,
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+                                uint32_t *ecx, uint32_t *edx)
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+{
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+    uint32_t l3_cores;
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+    assert(cache->size == cache->line_size * cache->associativity *
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+                          cache->partitions * cache->sets);
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+
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+    *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
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+               (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
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+
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+    /* L3 is shared among multiple cores */
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+    if (cache->level == 3) {
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+        l3_cores = cores_in_core_complex(cs->nr_cores);
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+        *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
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+    } else {
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+        *eax |= ((cs->nr_threads - 1) << 14);
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+    }
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+
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+    assert(cache->line_size > 0);
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+    assert(cache->partitions > 0);
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+    assert(cache->associativity > 0);
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+    /* We don't implement fully-associative caches */
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+    assert(cache->associativity < cache->sets);
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+    *ebx = (cache->line_size - 1) |
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+           ((cache->partitions - 1) << 12) |
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+           ((cache->associativity - 1) << 22);
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+
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+    assert(cache->sets > 0);
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+    *ecx = cache->sets - 1;
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+
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+    *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
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+           (cache->inclusive ? CACHE_INCLUSIVE : 0) |
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+           (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
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+}
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+
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+/*
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  * Definitions of the hardcoded cache entries we expose:
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  * These are legacy cache values. If there is a need to change any
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  * of these values please use builtin_x86_defs
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@@ -3988,6 +4081,30 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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             *edx = 0;
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         }
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         break;
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+    case 0x8000001D:
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+        *eax = 0;
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+        switch (count) {
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+        case 0: /* L1 dcache info */
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+            encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
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+                                       eax, ebx, ecx, edx);
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+            break;
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+        case 1: /* L1 icache info */
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+            encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
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+                                       eax, ebx, ecx, edx);
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+            break;
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+        case 2: /* L2 cache info */
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+            encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
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+                                       eax, ebx, ecx, edx);
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+            break;
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+        case 3: /* L3 cache info */
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+            encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
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+                                       eax, ebx, ecx, edx);
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+            break;
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+        default: /* end of info */
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+            *eax = *ebx = *ecx = *edx = 0;
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+            break;
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+        }
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+        break;
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     case 0xC0000000:
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         *eax = env->cpuid_xlevel2;
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         *ebx = 0;
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diff --git a/target/i386/kvm.c b/target/i386/kvm.c
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index 6c49954..6e66f9c 100644
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--- a/target/i386/kvm.c
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+++ b/target/i386/kvm.c
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@@ -967,9 +967,32 @@ int kvm_arch_init_vcpu(CPUState *cs)
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         }
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         c = &cpuid_data.entries[cpuid_i++];
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-        c->function = i;
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-        c->flags = 0;
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-        cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
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+        switch (i) {
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+        case 0x8000001d:
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+            /* Query for all AMD cache information leaves */
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+            for (j = 0; ; j++) {
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+                c->function = i;
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+                c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
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+                c->index = j;
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+                cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
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+
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+                if (c->eax == 0) {
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+                    break;
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+                }
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+                if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
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+                    fprintf(stderr, "cpuid_data is full, no space for "
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+                            "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
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+                    abort();
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+                }
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+                c = &cpuid_data.entries[cpuid_i++];
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+            }
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+            break;
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+        default:
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+            c->function = i;
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+            c->flags = 0;
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+            cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
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+            break;
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+        }
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     }
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     /* Call Centaur's CPUID instructions they are supported. */
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-- 
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1.8.3.1
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