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Blame SOURCES/kvm-i386-Define-the-Virt-SSBD-MSR-and-handling-of-it-CVE.patch

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From eba382cf6a9a9b0003f10ac3da3e638d6f70d492 Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Wed, 13 Jun 2018 18:50:55 +0200
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Subject: [PATCH 03/17] i386: Define the Virt SSBD MSR and handling of it
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 (CVE-2018-3639)
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <20180613185056.18066-2-ehabkost@redhat.com>
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Patchwork-id: 80679
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O-Subject: [RHEL-7.5 qemu-kvm PATCH 1/2] i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639)
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Bugzilla: 1584583
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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"Some AMD processors only support a non-architectural means of enabling
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speculative store bypass disable (SSBD).  To allow a simplified view of
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this to a guest, an architectural definition has been created through a new
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CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f.  With this, a
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hypervisor can virtualize the existence of this definition and provide an
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architectural method for using SSBD to a guest.
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Add the new CPUID feature, the new MSR and update the existing SSBD
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support to use this MSR when present." (from x86/speculation: Add virtualized
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speculative store bypass disable support in Linux).
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Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
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Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
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Message-Id: <20180521215424.13520-4-berrange@redhat.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit cfeea0c021db6234c154dbc723730e81553924ff)
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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Conflicts:
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    target-i386/kvm.c (MSR code)
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    target-i386/machine.c (trivial change from
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        VMStateDescription.needed to VMStateSubsection.needed)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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---
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 target-i386/cpu.h     |  2 ++
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 target-i386/kvm.c     | 17 +++++++++++++++--
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 target-i386/machine.c | 21 +++++++++++++++++++++
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 3 files changed, 38 insertions(+), 2 deletions(-)
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diff --git a/target-i386/cpu.h b/target-i386/cpu.h
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index c72b545..debb0e5 100644
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--- a/target-i386/cpu.h
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+++ b/target-i386/cpu.h
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@@ -305,6 +305,7 @@
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 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
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 #define MSR_TSC_ADJUST                  0x0000003b
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 #define MSR_IA32_SPEC_CTRL              0x48
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+#define MSR_VIRT_SSBD                   0xc001011f
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 #define MSR_IA32_TSCDEADLINE            0x6e0
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 #define MSR_P6_PERFCTR0                 0xc1
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@@ -1052,6 +1053,7 @@ typedef struct CPUX86State {
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     uint32_t pkru;
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     uint64_t spec_ctrl;
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+    uint64_t virt_ssbd;
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     TPRAccess tpr_access_type;
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 } CPUX86State;
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diff --git a/target-i386/kvm.c b/target-i386/kvm.c
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index a1a49d8..35a9cf4 100644
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--- a/target-i386/kvm.c
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+++ b/target-i386/kvm.c
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@@ -78,6 +78,7 @@ static bool has_msr_hv_tsc;
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 static bool has_msr_mtrr;
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 static bool has_msr_xss;
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 static bool has_msr_spec_ctrl;
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+static bool has_msr_virt_ssbd;
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 static bool has_msr_architectural_pmu;
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 static uint32_t num_architectural_pmu_counters;
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@@ -805,6 +806,10 @@ static int kvm_get_supported_msrs(KVMState *s)
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                     has_msr_spec_ctrl = true;
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                     continue;
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                 }
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+                if (kvm_msr_list->indices[i] == MSR_VIRT_SSBD) {
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+                    has_msr_virt_ssbd = true;
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+                    continue;
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+                }
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             }
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         }
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@@ -1217,6 +1222,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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     if (has_msr_spec_ctrl) {
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         kvm_msr_entry_set(&msrs[n++], MSR_IA32_SPEC_CTRL, env->spec_ctrl);
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     }
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+    if (has_msr_virt_ssbd) {
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+        kvm_msr_entry_set(&msrs[n++], MSR_VIRT_SSBD, env->virt_ssbd);
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+    }
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+
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 #ifdef TARGET_X86_64
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     if (lm_capable_kernel) {
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         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
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@@ -1577,8 +1586,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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     if (has_msr_spec_ctrl) {
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         msrs[n++].index = MSR_IA32_SPEC_CTRL;
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     }
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-
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-
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+    if (has_msr_virt_ssbd) {
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+        msrs[n++].index = MSR_VIRT_SSBD;
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+    }
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     if (!env->tsc_valid) {
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         msrs[n++].index = MSR_IA32_TSC;
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         env->tsc_valid = !runstate_is_running();
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@@ -1822,6 +1832,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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         case MSR_IA32_SPEC_CTRL:
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             env->spec_ctrl = msrs[i].data;
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             break;
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+        case MSR_VIRT_SSBD:
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+            env->virt_ssbd = msrs[i].data;
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+            break;
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         }
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     }
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diff --git a/target-i386/machine.c b/target-i386/machine.c
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index d883c86..507ab1a 100644
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--- a/target-i386/machine.c
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+++ b/target-i386/machine.c
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@@ -760,6 +760,24 @@ static const VMStateDescription vmstate_spec_ctrl = {
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     }
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 };
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+static bool virt_ssbd_needed(void *opaque)
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+{
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+    X86CPU *cpu = opaque;
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+    CPUX86State *env = &cpu->env;
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+
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+    return env->virt_ssbd != 0;
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+}
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+
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+static const VMStateDescription vmstate_msr_virt_ssbd = {
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+    .name = "cpu/virt_ssbd",
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+    .version_id = 1,
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+    .minimum_version_id = 1,
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+    .fields = (VMStateField[]){
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+        VMSTATE_UINT64(env.virt_ssbd, X86CPU),
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+        VMSTATE_END_OF_LIST()
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+    }
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+};
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+
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 const VMStateDescription vmstate_x86_cpu = {
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     .name = "cpu",
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     .version_id = 12,
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@@ -917,6 +935,9 @@ const VMStateDescription vmstate_x86_cpu = {
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         }, {
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             .vmsd = &vmstate_spec_ctrl,
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             .needed = spec_ctrl_needed,
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+        }, {
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+            .vmsd = &vmstate_msr_virt_ssbd,
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+            .needed = virt_ssbd_needed,
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         } , {
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             /* empty */
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         }
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-- 
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1.8.3.1
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