cryptospore / rpms / qemu-kvm

Forked from rpms/qemu-kvm 2 years ago
Clone
619821
From 18e92ed681383c787912d0cd4b8164d8e7df26d4 Mon Sep 17 00:00:00 2001
b28c64
From: Fam Zheng <famz@redhat.com>
619821
Date: Thu, 18 May 2017 09:21:15 +0200
b28c64
Subject: [PATCH 02/18] char/serial: Use generic Fifo8
b28c64
b28c64
RH-Author: Fam Zheng <famz@redhat.com>
619821
Message-id: <20170518092131.16571-3-famz@redhat.com>
619821
Patchwork-id: 75292
619821
O-Subject: [RHEL-7.4 qemu-kvm PATCH v3 02/18] char/serial: Use generic Fifo8
619821
Bugzilla: 1451470
b28c64
RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
619821
RH-Acked-by: Stefan Hajnoczi <stefanha@redhat.com>
b28c64
RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
b28c64
b28c64
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
b28c64
b28c64
Use the generic Fifo8 helper provided by QEMU, rather than re-implement
b28c64
privately.
b28c64
b28c64
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
b28c64
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
b28c64
(cherry picked from commit 8e8638fa87ff045f5dadec7342301bf10de776ff)
b28c64
Signed-off-by: Fam Zheng <famz@redhat.com>
b28c64
Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
b28c64
b28c64
Conflicts:
b28c64
	hw/char/serial.c
b28c64
Conflict because in downstream we've got 4df7961faa out of order.
b28c64
---
b28c64
 hw/char/serial.c         | 98 +++++++++++++++++-------------------------------
b28c64
 include/hw/char/serial.h | 15 +++-----
b28c64
 2 files changed, 39 insertions(+), 74 deletions(-)
b28c64
b28c64
diff --git a/hw/char/serial.c b/hw/char/serial.c
b28c64
index 7866b0f..0d4450e 100644
b28c64
--- a/hw/char/serial.c
b28c64
+++ b/hw/char/serial.c
b28c64
@@ -93,8 +93,6 @@
b28c64
 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
b28c64
 #define UART_FCR_FE         0x01    /* FIFO Enable */
b28c64
 
b28c64
-#define XMIT_FIFO           0
b28c64
-#define RECV_FIFO           1
b28c64
 #define MAX_XMIT_RETRY      4
b28c64
 
b28c64
 #ifdef DEBUG_SERIAL
b28c64
@@ -107,50 +105,14 @@ do {} while (0)
b28c64
 
b28c64
 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
b28c64
 
b28c64
-static void fifo_clear(SerialState *s, int fifo)
b28c64
+static inline void recv_fifo_put(SerialState *s, uint8_t chr)
b28c64
 {
b28c64
-    SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
b28c64
-    memset(f->data, 0, UART_FIFO_LENGTH);
b28c64
-    f->count = 0;
b28c64
-    f->head = 0;
b28c64
-    f->tail = 0;
b28c64
-}
b28c64
-
b28c64
-static int fifo_put(SerialState *s, int fifo, uint8_t chr)
b28c64
-{
b28c64
-    SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
b28c64
-
b28c64
     /* Receive overruns do not overwrite FIFO contents. */
b28c64
-    if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) {
b28c64
-
b28c64
-        f->data[f->head++] = chr;
b28c64
-
b28c64
-        if (f->head == UART_FIFO_LENGTH)
b28c64
-            f->head = 0;
b28c64
-    }
b28c64
-
b28c64
-    if (f->count < UART_FIFO_LENGTH)
b28c64
-        f->count++;
b28c64
-    else if (fifo == RECV_FIFO)
b28c64
+    if (!fifo8_is_full(&s->recv_fifo)) {
b28c64
+        fifo8_push(&s->recv_fifo, chr);
b28c64
+    } else {
b28c64
         s->lsr |= UART_LSR_OE;
b28c64
-
b28c64
-    return 1;
b28c64
-}
b28c64
-
b28c64
-static uint8_t fifo_get(SerialState *s, int fifo)
b28c64
-{
b28c64
-    SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
b28c64
-    uint8_t c;
b28c64
-
b28c64
-    if(f->count == 0)
b28c64
-        return 0;
b28c64
-
b28c64
-    c = f->data[f->tail++];
b28c64
-    if (f->tail == UART_FIFO_LENGTH)
b28c64
-        f->tail = 0;
b28c64
-    f->count--;
b28c64
-
b28c64
-    return c;
b28c64
+    }
b28c64
 }
b28c64
 
b28c64
 static void serial_update_irq(SerialState *s)
b28c64
@@ -166,7 +128,7 @@ static void serial_update_irq(SerialState *s)
b28c64
         tmp_iir = UART_IIR_CTI;
b28c64
     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
b28c64
                (!(s->fcr & UART_FCR_FE) ||
b28c64
-                s->recv_fifo.count >= s->recv_fifo.itl)) {
b28c64
+                s->recv_fifo.num >= s->recv_fifo_itl)) {
b28c64
         tmp_iir = UART_IIR_RDI;
b28c64
     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
b28c64
         tmp_iir = UART_IIR_THRI;
b28c64
@@ -263,8 +225,9 @@ static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque)
b28c64
 
b28c64
     if (s->tsr_retry <= 0) {
b28c64
         if (s->fcr & UART_FCR_FE) {
b28c64
-            s->tsr = fifo_get(s,XMIT_FIFO);
b28c64
-            if (!s->xmit_fifo.count) {
b28c64
+            s->tsr = fifo8_is_full(&s->xmit_fifo) ?
b28c64
+                        0 : fifo8_pop(&s->xmit_fifo);
b28c64
+            if (!s->xmit_fifo.num) {
b28c64
                 s->lsr |= UART_LSR_THRE;
b28c64
             }
b28c64
         } else if ((s->lsr & UART_LSR_THRE)) {
b28c64
@@ -318,7 +281,11 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
b28c64
         } else {
b28c64
             s->thr = (uint8_t) val;
b28c64
             if(s->fcr & UART_FCR_FE) {
b28c64
-                fifo_put(s, XMIT_FIFO, s->thr);
b28c64
+                /* xmit overruns overwrite data, so make space if needed */
b28c64
+                if (fifo8_is_full(&s->xmit_fifo)) {
b28c64
+                    fifo8_pop(&s->xmit_fifo);
b28c64
+                }
b28c64
+                fifo8_push(&s->xmit_fifo, s->thr);
b28c64
                 s->thr_ipending = 0;
b28c64
                 s->lsr &= ~UART_LSR_TEMT;
b28c64
                 s->lsr &= ~UART_LSR_THRE;
b28c64
@@ -369,28 +336,28 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
b28c64
         if (val & UART_FCR_RFR) {
b28c64
             qemu_del_timer(s->fifo_timeout_timer);
b28c64
             s->timeout_ipending=0;
b28c64
-            fifo_clear(s,RECV_FIFO);
b28c64
+            fifo8_reset(&s->recv_fifo);
b28c64
         }
b28c64
 
b28c64
         if (val & UART_FCR_XFR) {
b28c64
-            fifo_clear(s,XMIT_FIFO);
b28c64
+            fifo8_reset(&s->xmit_fifo);
b28c64
         }
b28c64
 
b28c64
         if (val & UART_FCR_FE) {
b28c64
             s->iir |= UART_IIR_FE;
b28c64
-            /* Set RECV_FIFO trigger Level */
b28c64
+            /* Set recv_fifo trigger Level */
b28c64
             switch (val & 0xC0) {
b28c64
             case UART_FCR_ITL_1:
b28c64
-                s->recv_fifo.itl = 1;
b28c64
+                s->recv_fifo_itl = 1;
b28c64
                 break;
b28c64
             case UART_FCR_ITL_2:
b28c64
-                s->recv_fifo.itl = 4;
b28c64
+                s->recv_fifo_itl = 4;
b28c64
                 break;
b28c64
             case UART_FCR_ITL_3:
b28c64
-                s->recv_fifo.itl = 8;
b28c64
+                s->recv_fifo_itl = 8;
b28c64
                 break;
b28c64
             case UART_FCR_ITL_4:
b28c64
-                s->recv_fifo.itl = 14;
b28c64
+                s->recv_fifo_itl = 14;
b28c64
                 break;
b28c64
             }
b28c64
         } else
b28c64
@@ -462,8 +429,9 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
b28c64
             ret = s->divider & 0xff;
b28c64
         } else {
b28c64
             if(s->fcr & UART_FCR_FE) {
b28c64
-                ret = fifo_get(s,RECV_FIFO);
b28c64
-                if (s->recv_fifo.count == 0) {
b28c64
+                ret = fifo8_is_full(&s->recv_fifo) ?
b28c64
+                            0 : fifo8_pop(&s->recv_fifo);
b28c64
+                if (s->recv_fifo.num == 0) {
b28c64
                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
b28c64
                 } else {
b28c64
                     qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
b28c64
@@ -537,7 +505,7 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
b28c64
 static int serial_can_receive(SerialState *s)
b28c64
 {
b28c64
     if(s->fcr & UART_FCR_FE) {
b28c64
-        if (s->recv_fifo.count < UART_FIFO_LENGTH) {
b28c64
+        if (s->recv_fifo.num < UART_FIFO_LENGTH) {
b28c64
             /*
b28c64
              * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
b28c64
              * if above. If UART_FIFO_LENGTH - fifo.count is advertised the
b28c64
@@ -545,8 +513,8 @@ static int serial_can_receive(SerialState *s)
b28c64
              * the guest has a chance to respond, effectively overriding the ITL
b28c64
              * that the guest has set.
b28c64
              */
b28c64
-            return (s->recv_fifo.count <= s->recv_fifo.itl) ?
b28c64
-                        s->recv_fifo.itl - s->recv_fifo.count : 1;
b28c64
+            return (s->recv_fifo.num <= s->recv_fifo_itl) ?
b28c64
+                        s->recv_fifo_itl - s->recv_fifo.num : 1;
b28c64
         } else {
b28c64
             return 0;
b28c64
         }
b28c64
@@ -559,7 +527,7 @@ static void serial_receive_break(SerialState *s)
b28c64
 {
b28c64
     s->rbr = 0;
b28c64
     /* When the LSR_DR is set a null byte is pushed into the fifo */
b28c64
-    fifo_put(s, RECV_FIFO, '\0');
b28c64
+    recv_fifo_put(s, '\0');
b28c64
     s->lsr |= UART_LSR_BI | UART_LSR_DR;
b28c64
     serial_update_irq(s);
b28c64
 }
b28c64
@@ -567,7 +535,7 @@ static void serial_receive_break(SerialState *s)
b28c64
 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
b28c64
 static void fifo_timeout_int (void *opaque) {
b28c64
     SerialState *s = opaque;
b28c64
-    if (s->recv_fifo.count) {
b28c64
+    if (s->recv_fifo.num) {
b28c64
         s->timeout_ipending = 1;
b28c64
         serial_update_irq(s);
b28c64
     }
b28c64
@@ -589,7 +557,7 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size)
b28c64
     if(s->fcr & UART_FCR_FE) {
b28c64
         int i;
b28c64
         for (i = 0; i < size; i++) {
b28c64
-            fifo_put(s, RECV_FIFO, buf[i]);
b28c64
+            recv_fifo_put(s, buf[i]);
b28c64
         }
b28c64
         s->lsr |= UART_LSR_DR;
b28c64
         /* call the timeout receive callback in 4 char transmit time */
b28c64
@@ -669,8 +637,8 @@ static void serial_reset(void *opaque)
b28c64
     s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
b28c64
     s->poll_msl = 0;
b28c64
 
b28c64
-    fifo_clear(s,RECV_FIFO);
b28c64
-    fifo_clear(s,XMIT_FIFO);
b28c64
+    fifo8_reset(&s->recv_fifo);
b28c64
+    fifo8_reset(&s->xmit_fifo);
b28c64
 
b28c64
     s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
b28c64
 
b28c64
@@ -693,6 +661,8 @@ void serial_init_core(SerialState *s)
b28c64
 
b28c64
     qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
b28c64
                           serial_event, s);
b28c64
+    fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
b28c64
+    fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
b28c64
     serial_reset(s);
b28c64
 }
b28c64
 
b28c64
diff --git a/include/hw/char/serial.h b/include/hw/char/serial.h
b28c64
index bca79f1..9ab81f6 100644
b28c64
--- a/include/hw/char/serial.h
b28c64
+++ b/include/hw/char/serial.h
b28c64
@@ -28,17 +28,10 @@
b28c64
 #include "hw/hw.h"
b28c64
 #include "sysemu/sysemu.h"
b28c64
 #include "exec/memory.h"
b28c64
+#include "qemu/fifo8.h"
b28c64
 
b28c64
 #define UART_FIFO_LENGTH    16      /* 16550A Fifo Length */
b28c64
 
b28c64
-typedef struct SerialFIFO {
b28c64
-    uint8_t data[UART_FIFO_LENGTH];
b28c64
-    uint8_t count;
b28c64
-    uint8_t itl;                        /* Interrupt Trigger Level */
b28c64
-    uint8_t tail;
b28c64
-    uint8_t head;
b28c64
-} SerialFIFO;
b28c64
-
b28c64
 struct SerialState {
b28c64
     uint16_t divider;
b28c64
     uint8_t rbr; /* receive register */
b28c64
@@ -67,8 +60,10 @@ struct SerialState {
b28c64
 
b28c64
     /* Time when the last byte was successfully sent out of the tsr */
b28c64
     uint64_t last_xmit_ts;
b28c64
-    SerialFIFO recv_fifo;
b28c64
-    SerialFIFO xmit_fifo;
b28c64
+    Fifo8 recv_fifo;
b28c64
+    Fifo8 xmit_fifo;
b28c64
+    /* Interrupt trigger level for recv_fifo */
b28c64
+    uint8_t recv_fifo_itl;
b28c64
 
b28c64
     struct QEMUTimer *fifo_timeout_timer;
b28c64
     int timeout_ipending;           /* timeout interrupt pending state */
b28c64
-- 
b28c64
1.8.3.1
b28c64