anitazha / rpms / ndctl

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From 7eb06a5293531854e7a28666e955106094d3552b Mon Sep 17 00:00:00 2001
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From: Dan Williams <dan.j.williams@intel.com>
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Date: Sun, 23 Jan 2022 16:53:29 -0800
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Subject: [PATCH 105/217] cxl/list: Add endpoints
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Endpoints are port-like objects that represent the HDM decoders at terminal
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end of a decode chain. Unlike port decoders that route to downstream ports,
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endpoint decoders route to endpoint DPA (Device Physical Address) ranges.
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Link: https://lore.kernel.org/r/164298560917.3021641.13753578554905796298.stgit@dwillia2-desk3.amr.corp.intel.com
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Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
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---
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 .clang-format                    |   1 +
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 Documentation/cxl/cxl-list.txt   |  16 ++++
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 Documentation/cxl/lib/libcxl.txt |  31 ++++++-
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 cxl/filter.c                     | 147 ++++++++++++++++++++++++++++---
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 cxl/filter.h                     |   2 +
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 cxl/json.c                       |  20 ++++-
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 cxl/json.h                       |   2 +
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 cxl/lib/libcxl.c                 | 107 ++++++++++++++++++++++
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 cxl/lib/libcxl.sym               |   9 ++
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 cxl/lib/private.h                |  10 +++
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 cxl/libcxl.h                     |  15 ++++
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 cxl/list.c                       |  13 ++-
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 12 files changed, 355 insertions(+), 18 deletions(-)
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diff --git a/.clang-format b/.clang-format
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index 391cd34..106bc5e 100644
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--- a/.clang-format
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+++ b/.clang-format
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@@ -80,6 +80,7 @@ ForEachMacros:
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   - 'cxl_memdev_foreach'
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   - 'cxl_bus_foreach'
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   - 'cxl_port_foreach'
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+  - 'cxl_endpoint_foreach'
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   - 'daxctl_dev_foreach'
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   - 'daxctl_mapping_foreach'
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   - 'daxctl_region_foreach'
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diff --git a/Documentation/cxl/cxl-list.txt b/Documentation/cxl/cxl-list.txt
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index 42b6de6..d342da2 100644
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--- a/Documentation/cxl/cxl-list.txt
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+++ b/Documentation/cxl/cxl-list.txt
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@@ -190,6 +190,12 @@ OPTIONS
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 ----
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 # cxl list -B
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 # cxl list -P -p root
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+----
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+	Additionally, endpoint objects are also ports so the following commands
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+	are also equivalent.
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+----
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+# cxl list -E
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+# cxl list -P -p endpoint
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 ----
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 	By default, only 'switch' ports are listed.
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@@ -200,6 +206,16 @@ OPTIONS
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 	descendants of the individual ports that match the filter. By default
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 	all descendant objects are listed.
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+-E::
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+--endpoints::
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+	Include endpoint objects (CXL Memory Device decoders) in the
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+	listing.
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+
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+-e::
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+--endpoint::
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+	Specify CXL endpoint device name(s), or device id(s) to filter
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+	the emitted endpoint(s).
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+
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 --debug::
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 	If the cxl tool was built with debug enabled, turn on debug
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 	messages.
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diff --git a/Documentation/cxl/lib/libcxl.txt b/Documentation/cxl/lib/libcxl.txt
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index 804e9ca..eebab37 100644
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--- a/Documentation/cxl/lib/libcxl.txt
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+++ b/Documentation/cxl/lib/libcxl.txt
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@@ -199,12 +199,41 @@ int cxl_port_get_id(struct cxl_port *port);
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 int cxl_port_is_enabled(struct cxl_port *port);
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 bool cxl_port_is_root(struct cxl_port *port);
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 bool cxl_port_is_switch(struct cxl_port *port);
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+bool cxl_port_is_endpoint(struct cxl_port *port);
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 ----
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 The port type is communicated via cxl_port_is_<type>(). An 'enabled' port
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 is one that has succeeded in discovering the CXL component registers in
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 the host device and has enumerated its downstream ports. In order for a
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 memdev to be enabled for CXL memory operation all CXL ports in its
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-ancestry must also be enabled.
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+ancestry must also be enabled including a root port, an arbitrary number
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+of intervening switch ports, and a terminal endpoint port.
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+
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+ENDPOINTS
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+---------
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+CXL endpoint objects encapsulate the set of host-managed device-memory
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+(HDM) decoders in a physical memory device. The endpoint is the last hop
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+in a decoder chain that translate SPA to DPA (system-physical-address to
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+device-local-physical-address).
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+
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+=== ENDPOINT: Enumeration
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+----
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+struct cxl_endpoint *cxl_endpoint_get_first(struct cxl_port *parent);
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+struct cxl_endpoint *cxl_endpoint_get_next(struct cxl_endpoint *endpoint);
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+struct cxl_ctx *cxl_endpoint_get_ctx(struct cxl_endpoint *endpoint);
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+struct cxl_port *cxl_endpoint_get_parent(struct cxl_endpoint *endpoint);
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+struct cxl_port *cxl_endpoint_get_port(struct cxl_endpoint *endpoint);
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+
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+#define cxl_endpoint_foreach(port, endpoint)                                 \
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+       for (endpoint = cxl_endpoint_get_first(port); endpoint != NULL;       \
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+            endpoint = cxl_endpoint_get_next(endpoint))
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+----
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+
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+=== ENDPOINT: Attributes
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+----
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+const char *cxl_endpoint_get_devname(struct cxl_endpoint *endpoint);
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+int cxl_endpoint_get_id(struct cxl_endpoint *endpoint);
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+int cxl_endpoint_is_enabled(struct cxl_endpoint *endpoint);
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+----
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 include::../../copyright.txt[]
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diff --git a/cxl/filter.c b/cxl/filter.c
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index 32171a4..5d80d1b 100644
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--- a/cxl/filter.c
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+++ b/cxl/filter.c
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@@ -47,8 +47,42 @@ bool cxl_filter_has(const char *__filter, const char *needle)
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 	return false;
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 }
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+static struct cxl_endpoint *
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+util_cxl_endpoint_filter(struct cxl_endpoint *endpoint, const char *__ident)
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+{
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+	char *ident, *save;
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+	const char *arg;
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+	int endpoint_id;
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+
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+	if (!__ident)
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+		return endpoint;
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+
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+	ident = strdup(__ident);
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+	if (!ident)
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+		return NULL;
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+
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+	for (arg = strtok_r(ident, which_sep(__ident), &save); arg;
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+	     arg = strtok_r(NULL, which_sep(__ident), &save)) {
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+		if (strcmp(arg, "all") == 0)
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+			break;
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+
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+		if ((sscanf(arg, "%d", &endpoint_id) == 1 ||
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+		     sscanf(arg, "endpoint%d", &endpoint_id) == 1) &&
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+		    cxl_endpoint_get_id(endpoint) == endpoint_id)
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+			break;
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+
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+		if (strcmp(arg, cxl_endpoint_get_devname(endpoint)) == 0)
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+			break;
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+	}
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+
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+	free(ident);
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+	if (arg)
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+		return endpoint;
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+	return NULL;
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+}
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+
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 static struct cxl_port *__util_cxl_port_filter(struct cxl_port *port,
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-					     const char *__ident)
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+					       const char *__ident)
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 {
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 	char *ident, *save;
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 	const char *arg;
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@@ -72,6 +106,9 @@ static struct cxl_port *__util_cxl_port_filter(struct cxl_port *port,
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 		if (strcmp(arg, "switch") == 0 && cxl_port_is_switch(port))
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 			break;
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+		if (strcmp(arg, "endpoint") == 0 && cxl_port_is_endpoint(port))
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+			break;
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+
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 		if ((sscanf(arg, "%d", &port_id) == 1 ||
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 		     sscanf(arg, "port%d", &port_id) == 1) &&
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 		    cxl_port_get_id(port) == port_id)
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@@ -116,6 +153,24 @@ static struct cxl_port *util_cxl_port_filter(struct cxl_port *port,
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 	return NULL;
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 }
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+static struct cxl_endpoint *
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+util_cxl_endpoint_filter_by_port(struct cxl_endpoint *endpoint,
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+				 const char *ident,
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+				 enum cxl_port_filter_mode mode)
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+{
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+	struct cxl_port *iter = cxl_endpoint_get_port(endpoint);
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+
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+	if (util_cxl_port_filter(iter, ident, CXL_PF_SINGLE))
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+		return endpoint;
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+	iter = cxl_port_get_parent(iter);
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+	if (!iter)
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+		return NULL;
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+	if (util_cxl_port_filter(iter, ident, mode))
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+		return endpoint;
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+
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+	return NULL;
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+}
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+
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 static struct cxl_bus *util_cxl_bus_filter(struct cxl_bus *bus,
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 					   const char *__ident)
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 {
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@@ -325,10 +380,34 @@ static struct json_object *pick_array(struct json_object *child,
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 	return NULL;
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 }
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+static void walk_endpoints(struct cxl_port *port, struct cxl_filter_params *p,
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+			   struct json_object *jeps, unsigned long flags)
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+{
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+	struct cxl_endpoint *endpoint;
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+
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+	cxl_endpoint_foreach(port, endpoint) {
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+		struct cxl_port *ep_port = cxl_endpoint_get_port(endpoint);
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+		struct json_object *jendpoint;
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+
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+		if (!util_cxl_endpoint_filter(endpoint, p->endpoint_filter))
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+			continue;
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+		if (!util_cxl_port_filter_by_bus(ep_port, p->bus_filter))
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+			continue;
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+		if (!util_cxl_endpoint_filter_by_port(endpoint, p->port_filter,
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+						      pf_mode(p)))
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+			continue;
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+		if (!p->idle && !cxl_endpoint_is_enabled(endpoint))
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+			continue;
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+		jendpoint = util_cxl_endpoint_to_json(endpoint, flags);
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+		if (jendpoint)
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+			json_object_array_add(jeps, jendpoint);
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+	}
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+}
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+
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 static void walk_child_ports(struct cxl_port *parent_port,
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 			     struct cxl_filter_params *p,
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 			     struct json_object *jports,
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-			     unsigned long flags)
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+			     struct json_object *jeps, unsigned long flags)
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 {
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 	struct cxl_port *port;
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@@ -336,6 +415,7 @@ static void walk_child_ports(struct cxl_port *parent_port,
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 		const char *devname = cxl_port_get_devname(port);
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 		struct json_object *jport = NULL;
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 		struct json_object *jchildports = NULL;
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+		struct json_object *jchildendpoints = NULL;
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 		if (!util_cxl_port_filter(port, p->port_filter, pf_mode(p)))
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 			goto walk_children;
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@@ -343,21 +423,41 @@ static void walk_child_ports(struct cxl_port *parent_port,
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 			goto walk_children;
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 		if (!p->idle && !cxl_port_is_enabled(port))
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 			continue;
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-		if (p->ports)
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+		if (p->ports) {
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 			jport = util_cxl_port_to_json(port, flags);
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-		if (!jport)
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-			continue;
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-		json_object_array_add(jports, jport);
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-		jchildports = json_object_new_array();
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-		if (!jchildports) {
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-			err(p, "%s: failed to enumerate child ports\n",
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-			    devname);
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-			continue;
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+			if (!jport) {
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+				err(p, "%s: failed to list\n", devname);
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+				continue;
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+			}
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+			json_object_array_add(jports, jport);
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+			jchildports = json_object_new_array();
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+			if (!jchildports) {
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+				err(p, "%s: failed to enumerate child ports\n",
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+				    devname);
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+				continue;
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+			}
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+		}
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+
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+		if (p->ports && p->endpoints) {
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+			jchildendpoints = json_object_new_array();
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+			if (!jchildendpoints) {
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+				err(p,
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+				    "%s: failed to enumerate child endpoints\n",
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+				    devname);
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+				continue;
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+			}
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 		}
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+
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 walk_children:
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+		if (p->endpoints)
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+			walk_endpoints(port, p, pick_array(jchildendpoints, jeps),
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+				       flags);
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+
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 		walk_child_ports(port, p, pick_array(jchildports, jports),
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-				 flags);
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+				 pick_array(jchildendpoints, jeps), flags);
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 		cond_add_put_array_suffix(jport, "ports", devname, jchildports);
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+		cond_add_put_array_suffix(jport, "endpoints", devname,
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+					  jchildendpoints);
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 	}
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 }
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@@ -366,6 +466,7 @@ int cxl_filter_walk(struct cxl_ctx *ctx, struct cxl_filter_params *p)
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 	struct json_object *jdevs = NULL, *jbuses = NULL, *jports = NULL;
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 	struct json_object *jplatform = json_object_new_array();
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 	unsigned long flags = params_to_flags(p);
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+	struct json_object *jeps = NULL;
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 	struct cxl_memdev *memdev;
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 	int top_level_objs = 0;
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 	struct cxl_bus *bus;
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@@ -387,6 +488,10 @@ int cxl_filter_walk(struct cxl_ctx *ctx, struct cxl_filter_params *p)
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 	if (!jports)
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 		goto err;
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+	jeps = json_object_new_array();
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+	if (!jeps)
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+		goto err;
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+
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 	dbg(p, "walk memdevs\n");
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 	cxl_memdev_foreach(ctx, memdev) {
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 		struct json_object *jdev;
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@@ -408,6 +513,7 @@ int cxl_filter_walk(struct cxl_ctx *ctx, struct cxl_filter_params *p)
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 	cxl_bus_foreach(ctx, bus) {
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 		struct json_object *jbus = NULL;
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 		struct json_object *jchildports = NULL;
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+		struct json_object *jchildeps = NULL;
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 		struct cxl_port *port = cxl_bus_get_port(bus);
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 		const char *devname = cxl_bus_get_devname(bus);
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@@ -431,12 +537,23 @@ int cxl_filter_walk(struct cxl_ctx *ctx, struct cxl_filter_params *p)
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 					continue;
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 				}
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 			}
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+			if (p->endpoints) {
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+				jchildeps = json_object_new_array();
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+				if (!jchildeps) {
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+					err(p,
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+					    "%s: failed to enumerate child endpoints\n",
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+					    devname);
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+					continue;
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+				}
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+			}
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 		}
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 walk_children:
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 		dbg(p, "walk ports\n");
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 		walk_child_ports(port, p, pick_array(jchildports, jports),
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-				 flags);
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+				 pick_array(jchildeps, jeps), flags);
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 		cond_add_put_array_suffix(jbus, "ports", devname, jchildports);
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+		cond_add_put_array_suffix(jbus, "endpoints", devname,
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+					  jchildeps);
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 	}
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 	if (json_object_array_length(jdevs))
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@@ -445,10 +562,13 @@ walk_children:
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 		top_level_objs++;
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 	if (json_object_array_length(jports))
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 		top_level_objs++;
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+	if (json_object_array_length(jeps))
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+		top_level_objs++;
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 	splice_array(p, jdevs, jplatform, "anon memdevs", top_level_objs > 1);
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 	splice_array(p, jbuses, jplatform, "buses", top_level_objs > 1);
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 	splice_array(p, jports, jplatform, "ports", top_level_objs > 1);
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+	splice_array(p, jeps, jplatform, "endpoints", top_level_objs > 1);
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 	util_display_json_array(stdout, jplatform, flags);
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@@ -457,6 +577,7 @@ err:
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 	json_object_put(jdevs);
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 	json_object_put(jbuses);
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 	json_object_put(jports);
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+	json_object_put(jeps);
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 	json_object_put(jplatform);
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 	return -ENOMEM;
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 }
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diff --git a/cxl/filter.h b/cxl/filter.h
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index 0d83304..bbd341c 100644
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--- a/cxl/filter.h
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+++ b/cxl/filter.h
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@@ -11,7 +11,9 @@ struct cxl_filter_params {
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 	const char *serial_filter;
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 	const char *bus_filter;
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 	const char *port_filter;
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+	const char *endpoint_filter;
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 	bool single;
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+	bool endpoints;
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 	bool memdevs;
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 	bool ports;
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 	bool buses;
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diff --git a/cxl/json.c b/cxl/json.c
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index d9f864e..08f6192 100644
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--- a/cxl/json.c
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+++ b/cxl/json.c
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@@ -243,8 +243,9 @@ struct json_object *util_cxl_bus_to_json(struct cxl_bus *bus,
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 	return jbus;
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 }
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-struct json_object *util_cxl_port_to_json(struct cxl_port *port,
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-					  unsigned long flags)
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+static struct json_object *__util_cxl_port_to_json(struct cxl_port *port,
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+						   const char *name_key,
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+						   unsigned long flags)
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 {
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 	const char *devname = cxl_port_get_devname(port);
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 	struct json_object *jport, *jobj;
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@@ -255,7 +256,7 @@ struct json_object *util_cxl_port_to_json(struct cxl_port *port,
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 	jobj = json_object_new_string(devname);
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 	if (jobj)
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-		json_object_object_add(jport, "port", jobj);
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+		json_object_object_add(jport, name_key, jobj);
e0018b
 
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 	if (!cxl_port_is_enabled(port)) {
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 		jobj = json_object_new_string("disabled");
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@@ -265,3 +266,16 @@ struct json_object *util_cxl_port_to_json(struct cxl_port *port,
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 	return jport;
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 }
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+
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+struct json_object *util_cxl_port_to_json(struct cxl_port *port,
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+					  unsigned long flags)
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+{
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+	return __util_cxl_port_to_json(port, "port", flags);
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+}
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+
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+struct json_object *util_cxl_endpoint_to_json(struct cxl_endpoint *endpoint,
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+					      unsigned long flags)
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+{
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+	return __util_cxl_port_to_json(cxl_endpoint_get_port(endpoint),
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+				       "endpoint", flags);
e0018b
+}
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diff --git a/cxl/json.h b/cxl/json.h
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index 36653db..8f45190 100644
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--- a/cxl/json.h
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+++ b/cxl/json.h
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@@ -11,4 +11,6 @@ struct json_object *util_cxl_bus_to_json(struct cxl_bus *bus,
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 struct cxl_port;
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 struct json_object *util_cxl_port_to_json(struct cxl_port *port,
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 					  unsigned long flags);
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+struct json_object *util_cxl_endpoint_to_json(struct cxl_endpoint *endpoint,
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+					      unsigned long flags);
e0018b
 #endif /* __CXL_UTIL_JSON_H__ */
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diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c
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index 03eff3c..a25e715 100644
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--- a/cxl/lib/libcxl.c
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+++ b/cxl/lib/libcxl.c
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@@ -67,14 +67,18 @@ static void free_memdev(struct cxl_memdev *memdev, struct list_head *head)
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 }
e0018b
 
e0018b
 static void free_port(struct cxl_port *port, struct list_head *head);
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+static void free_endpoint(struct cxl_endpoint *endpoint, struct list_head *head);
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 static void __free_port(struct cxl_port *port, struct list_head *head)
e0018b
 {
e0018b
 	struct cxl_port *child, *_c;
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+	struct cxl_endpoint *endpoint, *_e;
e0018b
 
e0018b
 	if (head)
e0018b
 		list_del_from(head, &port->list);
e0018b
 	list_for_each_safe(&port->child_ports, child, _c, list)
e0018b
 		free_port(child, &port->child_ports);
e0018b
+	list_for_each_safe(&port->endpoints, endpoint, _e, port.list)
e0018b
+		free_endpoint(endpoint, &port->endpoints);
e0018b
 	kmod_module_unref(port->module);
e0018b
 	free(port->dev_buf);
e0018b
 	free(port->dev_path);
e0018b
@@ -87,6 +91,12 @@ static void free_port(struct cxl_port *port, struct list_head *head)
e0018b
 	free(port);
e0018b
 }
e0018b
 
e0018b
+static void free_endpoint(struct cxl_endpoint *endpoint, struct list_head *head)
e0018b
+{
e0018b
+	__free_port(&endpoint->port, head);
e0018b
+	free(endpoint);
e0018b
+}
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+
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 static void free_bus(struct cxl_bus *bus, struct list_head *head)
e0018b
 {
e0018b
 	__free_port(&bus->port, head);
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@@ -500,6 +510,7 @@ static int cxl_port_init(struct cxl_port *port, struct cxl_port *parent_port,
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 	port->parent = parent_port;
e0018b
 
e0018b
 	list_head_init(&port->child_ports);
e0018b
+	list_head_init(&port->endpoints);
e0018b
 
e0018b
 	port->dev_path = strdup(cxlport_base);
e0018b
 	if (!port->dev_path)
e0018b
@@ -529,6 +540,97 @@ err:
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 	return -ENOMEM;
e0018b
 }
e0018b
 
e0018b
+static void *add_cxl_endpoint(void *parent, int id, const char *cxlep_base)
e0018b
+{
e0018b
+	const char *devname = devpath_to_devname(cxlep_base);
e0018b
+	struct cxl_endpoint *endpoint, *endpoint_dup;
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+	struct cxl_port *port = parent;
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+	struct cxl_ctx *ctx = cxl_port_get_ctx(port);
e0018b
+	int rc;
e0018b
+
e0018b
+	dbg(ctx, "%s: base: \'%s\'\n", devname, cxlep_base);
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+
e0018b
+	endpoint = calloc(1, sizeof(*endpoint));
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+	if (!endpoint)
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+		return NULL;
e0018b
+
e0018b
+	rc = cxl_port_init(&endpoint->port, port, CXL_PORT_ENDPOINT, ctx, id,
e0018b
+			   cxlep_base);
e0018b
+	if (rc)
e0018b
+		goto err;
e0018b
+
e0018b
+	cxl_endpoint_foreach(port, endpoint_dup)
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+		if (endpoint_dup->port.id == endpoint->port.id) {
e0018b
+			free_endpoint(endpoint, NULL);
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+			return endpoint_dup;
e0018b
+		}
e0018b
+
e0018b
+	list_add(&port->endpoints, &endpoint->port.list);
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+	return endpoint;
e0018b
+
e0018b
+err:
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+	free(endpoint);
e0018b
+	return NULL;
e0018b
+
e0018b
+}
e0018b
+
e0018b
+static void cxl_endpoints_init(struct cxl_port *port)
e0018b
+{
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+	struct cxl_ctx *ctx = cxl_port_get_ctx(port);
e0018b
+
e0018b
+	if (port->endpoints_init)
e0018b
+		return;
e0018b
+
e0018b
+	port->endpoints_init = 1;
e0018b
+
e0018b
+	sysfs_device_parse(ctx, port->dev_path, "endpoint", port,
e0018b
+			   add_cxl_endpoint);
e0018b
+}
e0018b
+
e0018b
+CXL_EXPORT struct cxl_ctx *cxl_endpoint_get_ctx(struct cxl_endpoint *endpoint)
e0018b
+{
e0018b
+	return endpoint->port.ctx;
e0018b
+}
e0018b
+
e0018b
+CXL_EXPORT struct cxl_endpoint *cxl_endpoint_get_first(struct cxl_port *port)
e0018b
+{
e0018b
+	cxl_endpoints_init(port);
e0018b
+
e0018b
+	return list_top(&port->endpoints, struct cxl_endpoint, port.list);
e0018b
+}
e0018b
+
e0018b
+CXL_EXPORT struct cxl_endpoint *cxl_endpoint_get_next(struct cxl_endpoint *endpoint)
e0018b
+{
e0018b
+	struct cxl_port *port = endpoint->port.parent;
e0018b
+
e0018b
+	return list_next(&port->endpoints, endpoint, port.list);
e0018b
+}
e0018b
+
e0018b
+CXL_EXPORT const char *cxl_endpoint_get_devname(struct cxl_endpoint *endpoint)
e0018b
+{
e0018b
+	return devpath_to_devname(endpoint->port.dev_path);
e0018b
+}
e0018b
+
e0018b
+CXL_EXPORT int cxl_endpoint_get_id(struct cxl_endpoint *endpoint)
e0018b
+{
e0018b
+	return endpoint->port.id;
e0018b
+}
e0018b
+
e0018b
+CXL_EXPORT struct cxl_port *cxl_endpoint_get_parent(struct cxl_endpoint *endpoint)
e0018b
+{
e0018b
+	return endpoint->port.parent;
e0018b
+}
e0018b
+
e0018b
+CXL_EXPORT struct cxl_port *cxl_endpoint_get_port(struct cxl_endpoint *endpoint)
e0018b
+{
e0018b
+	return &endpoint->port;
e0018b
+}
e0018b
+
e0018b
+CXL_EXPORT int cxl_endpoint_is_enabled(struct cxl_endpoint *endpoint)
e0018b
+{
e0018b
+	return cxl_port_is_enabled(&endpoint->port);
e0018b
+}
e0018b
+
e0018b
 static void *add_cxl_port(void *parent, int id, const char *cxlport_base)
e0018b
 {
e0018b
 	const char *devname = devpath_to_devname(cxlport_base);
e0018b
@@ -619,6 +721,11 @@ CXL_EXPORT bool cxl_port_is_switch(struct cxl_port *port)
e0018b
 	return port->type == CXL_PORT_SWITCH;
e0018b
 }
e0018b
 
e0018b
+CXL_EXPORT bool cxl_port_is_endpoint(struct cxl_port *port)
e0018b
+{
e0018b
+	return port->type == CXL_PORT_ENDPOINT;
e0018b
+}
e0018b
+
e0018b
 CXL_EXPORT struct cxl_bus *cxl_port_get_bus(struct cxl_port *port)
e0018b
 {
e0018b
 	struct cxl_bus *bus;
e0018b
diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym
e0018b
index a7e923f..7a51a0c 100644
e0018b
--- a/cxl/lib/libcxl.sym
e0018b
+++ b/cxl/lib/libcxl.sym
e0018b
@@ -93,5 +93,14 @@ global:
e0018b
 	cxl_port_is_root;
e0018b
 	cxl_port_is_switch;
e0018b
 	cxl_port_to_bus;
e0018b
+	cxl_port_is_endpoint;
e0018b
 	cxl_port_get_bus;
e0018b
+	cxl_endpoint_get_first;
e0018b
+	cxl_endpoint_get_next;
e0018b
+	cxl_endpoint_get_devname;
e0018b
+	cxl_endpoint_get_id;
e0018b
+	cxl_endpoint_get_ctx;
e0018b
+	cxl_endpoint_is_enabled;
e0018b
+	cxl_endpoint_get_parent;
e0018b
+	cxl_endpoint_get_port;
e0018b
 } LIBCXL_1;
e0018b
diff --git a/cxl/lib/private.h b/cxl/lib/private.h
e0018b
index 637f90d..cedd2f2 100644
e0018b
--- a/cxl/lib/private.h
e0018b
+++ b/cxl/lib/private.h
e0018b
@@ -17,6 +17,7 @@ struct cxl_pmem {
e0018b
 	char *dev_path;
e0018b
 };
e0018b
 
e0018b
+struct cxl_endpoint;
e0018b
 struct cxl_memdev {
e0018b
 	int id, major, minor;
e0018b
 	void *dev_buf;
e0018b
@@ -32,11 +33,13 @@ struct cxl_memdev {
e0018b
 	struct kmod_module *module;
e0018b
 	struct cxl_pmem *pmem;
e0018b
 	unsigned long long serial;
e0018b
+	struct cxl_endpoint *endpoint;
e0018b
 };
e0018b
 
e0018b
 enum cxl_port_type {
e0018b
 	CXL_PORT_ROOT,
e0018b
 	CXL_PORT_SWITCH,
e0018b
+	CXL_PORT_ENDPOINT,
e0018b
 };
e0018b
 
e0018b
 struct cxl_port {
e0018b
@@ -46,6 +49,7 @@ struct cxl_port {
e0018b
 	char *dev_path;
e0018b
 	char *uport;
e0018b
 	int ports_init;
e0018b
+	int endpoints_init;
e0018b
 	struct cxl_ctx *ctx;
e0018b
 	struct cxl_bus *bus;
e0018b
 	enum cxl_port_type type;
e0018b
@@ -53,12 +57,18 @@ struct cxl_port {
e0018b
 	struct kmod_module *module;
e0018b
 	struct list_node list;
e0018b
 	struct list_head child_ports;
e0018b
+	struct list_head endpoints;
e0018b
 };
e0018b
 
e0018b
 struct cxl_bus {
e0018b
 	struct cxl_port port;
e0018b
 };
e0018b
 
e0018b
+struct cxl_endpoint {
e0018b
+	struct cxl_port port;
e0018b
+	struct cxl_memdev *memdev;
e0018b
+};
e0018b
+
e0018b
 enum cxl_cmd_query_status {
e0018b
 	CXL_CMD_QUERY_NOT_RUN = 0,
e0018b
 	CXL_CMD_QUERY_OK,
e0018b
diff --git a/cxl/libcxl.h b/cxl/libcxl.h
e0018b
index efbb397..f6ba9a1 100644
e0018b
--- a/cxl/libcxl.h
e0018b
+++ b/cxl/libcxl.h
e0018b
@@ -81,12 +81,27 @@ struct cxl_port *cxl_port_get_parent(struct cxl_port *port);
e0018b
 bool cxl_port_is_root(struct cxl_port *port);
e0018b
 bool cxl_port_is_switch(struct cxl_port *port);
e0018b
 struct cxl_bus *cxl_port_to_bus(struct cxl_port *port);
e0018b
+bool cxl_port_is_endpoint(struct cxl_port *port);
e0018b
 struct cxl_bus *cxl_port_get_bus(struct cxl_port *port);
e0018b
 
e0018b
 #define cxl_port_foreach(parent, port)                                         \
e0018b
 	for (port = cxl_port_get_first(parent); port != NULL;                  \
e0018b
 	     port = cxl_port_get_next(port))
e0018b
 
e0018b
+struct cxl_endpoint;
e0018b
+struct cxl_endpoint *cxl_endpoint_get_first(struct cxl_port *parent);
e0018b
+struct cxl_endpoint *cxl_endpoint_get_next(struct cxl_endpoint *endpoint);
e0018b
+const char *cxl_endpoint_get_devname(struct cxl_endpoint *endpoint);
e0018b
+int cxl_endpoint_get_id(struct cxl_endpoint *endpoint);
e0018b
+struct cxl_ctx *cxl_endpoint_get_ctx(struct cxl_endpoint *endpoint);
e0018b
+int cxl_endpoint_is_enabled(struct cxl_endpoint *endpoint);
e0018b
+struct cxl_port *cxl_endpoint_get_parent(struct cxl_endpoint *endpoint);
e0018b
+struct cxl_port *cxl_endpoint_get_port(struct cxl_endpoint *endpoint);
e0018b
+
e0018b
+#define cxl_endpoint_foreach(port, endpoint)                                   \
e0018b
+	for (endpoint = cxl_endpoint_get_first(port); endpoint != NULL;        \
e0018b
+	     endpoint = cxl_endpoint_get_next(endpoint))
e0018b
+
e0018b
 struct cxl_cmd;
e0018b
 const char *cxl_cmd_get_devname(struct cxl_cmd *cmd);
e0018b
 struct cxl_cmd *cxl_cmd_new_raw(struct cxl_memdev *memdev, int opcode);
e0018b
diff --git a/cxl/list.c b/cxl/list.c
e0018b
index 01ab19b..b15e01c 100644
e0018b
--- a/cxl/list.c
e0018b
+++ b/cxl/list.c
e0018b
@@ -31,6 +31,11 @@ static const struct option options[] = {
e0018b
 	OPT_BOOLEAN('P', "ports", &param.ports, "include CXL port info"),
e0018b
 	OPT_BOOLEAN('S', "single", &param.single,
e0018b
 		    "skip listing descendant objects"),
e0018b
+	OPT_STRING('e', "endpoint", &param.endpoint_filter,
e0018b
+		   "endpoint device name",
e0018b
+		   "filter by CXL endpoint device name(s)"),
e0018b
+	OPT_BOOLEAN('E', "endpoints", &param.endpoints,
e0018b
+		    "include CXL endpoint info"),
e0018b
 	OPT_BOOLEAN('i', "idle", &param.idle, "include disabled devices"),
e0018b
 	OPT_BOOLEAN('u', "human", &param.human,
e0018b
 		    "use human friendly number formats "),
e0018b
@@ -44,7 +49,8 @@ static const struct option options[] = {
e0018b
 
e0018b
 static int num_list_flags(void)
e0018b
 {
e0018b
-       return !!param.memdevs + !!param.buses + !!param.ports;
e0018b
+	return !!param.memdevs + !!param.buses + !!param.ports +
e0018b
+	       !!param.endpoints;
e0018b
 }
e0018b
 
e0018b
 int cmd_list(int argc, const char **argv, struct cxl_ctx *ctx)
e0018b
@@ -74,6 +80,8 @@ int cmd_list(int argc, const char **argv, struct cxl_ctx *ctx)
e0018b
 			param.buses = true;
e0018b
 		if (param.port_filter)
e0018b
 			param.ports = true;
e0018b
+		if (param.endpoint_filter)
e0018b
+			param.endpoints = true;
e0018b
 		if (num_list_flags() == 0) {
e0018b
 			/*
e0018b
 			 * TODO: We likely want to list regions by default if
e0018b
@@ -96,6 +104,9 @@ int cmd_list(int argc, const char **argv, struct cxl_ctx *ctx)
e0018b
 	if (cxl_filter_has(param.port_filter, "root") && param.ports)
e0018b
 		param.buses = true;
e0018b
 
e0018b
+	if (cxl_filter_has(param.port_filter, "endpoint") && param.ports)
e0018b
+		param.endpoints = true;
e0018b
+
e0018b
 	dbg(&param, "walk topology\n");
e0018b
 	return cxl_filter_walk(ctx, ¶m;;
e0018b
 }
e0018b
-- 
e0018b
2.27.0
e0018b