Johnny Hughes
2019-02-04 c1f36c28393a7bb126cbf436cd6a4077a5b5c313
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From 329959e4e0ed9e8658ab84fa1df5b2225a623a3d Mon Sep 17 00:00:00 2001
From: Maxime Chevallier <maxime.chevallier@bootlin.com>
Date: Wed, 18 Apr 2018 11:14:44 +0200
Subject: [PATCH 44/46] net: mvpp2: Fix DMA address mask size
 
PPv2 TX/RX descriptors uses 40bits DMA addresses, but 41 bits masks were
used (GENMASK_ULL(40, 0)).
 
This commit fixes that by using the correct mask.
 
Fixes: e7c5359f2eed ("net: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors")
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit da42bb271305d68df6cbf99eed90542f1f1ee1c9)
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 drivers/net/ethernet/marvell/mvpp2.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)
 
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index 9deb79b..4202f9b 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -916,6 +916,8 @@ static struct {
 
 #define MVPP2_MIB_COUNTERS_STATS_DELAY        (1 * HZ)
 
+#define MVPP2_DESC_DMA_MASK    DMA_BIT_MASK(40)
+
 /* Definitions */
 
 /* Shared Packet Processor resources */
@@ -1429,7 +1431,7 @@ static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
     if (port->priv->hw_version == MVPP21)
         return tx_desc->pp21.buf_dma_addr;
     else
-        return tx_desc->pp22.buf_dma_addr_ptp & GENMASK_ULL(40, 0);
+        return tx_desc->pp22.buf_dma_addr_ptp & MVPP2_DESC_DMA_MASK;
 }
 
 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
@@ -1447,7 +1449,7 @@ static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
     } else {
         u64 val = (u64)addr;
 
-        tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
+        tx_desc->pp22.buf_dma_addr_ptp &= ~MVPP2_DESC_DMA_MASK;
         tx_desc->pp22.buf_dma_addr_ptp |= val;
         tx_desc->pp22.packet_offset = offset;
     }
@@ -1507,7 +1509,7 @@ static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
     if (port->priv->hw_version == MVPP21)
         return rx_desc->pp21.buf_dma_addr;
     else
-        return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
+        return rx_desc->pp22.buf_dma_addr_key_hash & MVPP2_DESC_DMA_MASK;
 }
 
 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
@@ -1516,7 +1518,7 @@ static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
     if (port->priv->hw_version == MVPP21)
         return rx_desc->pp21.buf_cookie;
     else
-        return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
+        return rx_desc->pp22.buf_cookie_misc & MVPP2_DESC_DMA_MASK;
 }
 
 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
@@ -8789,7 +8791,7 @@ static int mvpp2_probe(struct platform_device *pdev)
     }
 
     if (priv->hw_version == MVPP22) {
-        err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));
+        err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
         if (err)
             goto err_mg_clk;
         /* Sadly, the BM pools all share the same register to
-- 
2.7.4