Johnny Hughes
2019-02-04 c1f36c28393a7bb126cbf436cd6a4077a5b5c313
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From 3c9a17d64f5fb028a937b135ba4cfaa7e17fcce1 Mon Sep 17 00:00:00 2001
From: Khuong Dinh <khuong.dinh@amperecomputing.com>
Date: Mon, 30 Apr 2018 13:56:32 +0100
Subject: [PATCH 01/11] BACKPORT: arm64: cmpwait: Clear event register before
 arming exclusive monitor
 
When waiting for a cacheline to change state in cmpwait, we may immediately
wake-up the first time around the outer loop if the event register was
already set (for example, because of the event stream).
 
Avoid these spurious wakeups by explicitly clearing the event register
before loading the cacheline and setting the exclusive monitor.
 
This patch is required to fix kernel lock up due to new implementation of
queued read write locking from kernel 4.14.
This patch is backported from:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20180913&id=1cfc63b5ae60fe7e01773f38132f98d8b13a99a0
 
Change-Id: I1151172c53f0049a54dfae892ff423ab14b067e7
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Khuong Dinh <khuong.dinh@amperecomputing.com>
---
 arch/arm64/include/asm/cmpxchg.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
 
diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
index ae852ad..0f2e1ab 100644
--- a/arch/arm64/include/asm/cmpxchg.h
+++ b/arch/arm64/include/asm/cmpxchg.h
@@ -229,7 +229,9 @@
     unsigned long tmp;                        \
                                     \
     asm volatile(                            \
-    "    ldxr" #sz "\t%" #w "[tmp], %[v]\n"        \
+    "    sevl\n"                            \
+    "    wfe\n"                            \
+    "    ldxr" #sz "\t%" #w "[tmp], %[v]\n"            \
     "    eor    %" #w "[tmp], %" #w "[tmp], %" #w "[val]\n"    \
     "    cbnz    %" #w "[tmp], 1f\n"                \
     "    wfe\n"                            \
-- 
1.8.3.1